Hi,
I was wondering what happens if CPU and CLA are trying to access 'CLA to CPU Message RAM' at the same time. From the CLA data sheet, it says 'CLA write' has higher priority than 'CPU reads'.
Questions:
1. Does it mean 'CPU reads' request is ignored or 'CPU reads' will still happen but only after 'CLA write'?
2. If 'CPU_reads' occured slightly earlier than 'CLA write', how would 'CPU reads' be interrupted by 'CLA write'?
Thanks.