For a while now I've been strugging to locate the cause of analog noise spread across all 16 ADC channels on a DSP (TMS320F28335) we are using.
At first we suspected something else on the PCB (external SRAM/FPGA interconnects, ethernet controllers, switching power supplies, etc) may have been the cause, but I've tried a couple of development kits and seen similar noise (the TI C2000 experimenter kit with controlCARD F28335 had lower noise, but similar profile, and the Spectrum Digital eZdsp F28335 had slightly higher noise levels than that, very similar to our noise, but it may be poor due to the "clamshell socket" the chip is loaded in).
I've used Microsoft Excel to carry out some simple analysis (time and frequency domain) on samples dumped from memory. At the moment I'm having trouble trusting my results due to some interesting testing I've just performed.
Our Hardware:
TI TMS320F28335 (BGA package) running at 150MHz off 3V3 and 1V9 supplies, ADC using the internal reference (unable to test with external reference due to ADCREFIN on the BGA pad being directly grounded).
ISSI IS61WV102416 1M x 16 External SRAM
Altera Cyclone II FPGA
Various other digital chips including Ethercat and Ethernet controllers.
Various analog chips including op-amp signal conditioners (amplifiers, filters, level translators) and an analog mux for low priority analog signals.
We have a common ground for the whole PCB with split analog and digital 5V/3V3/1V9 power rails with EMI filters between the analog and digital, with bypass capacitors placed as close as possible below the ADC section of the BGA.
About the only real problems/differences I can spot with our design are:
- 4.7uF capacitors on ADCREFP/ADCREFM instead of 2.2uF.
- Not as many ferrites on the analog and digital DSP voltage rails (there appear to be inductor/capacitor pairs per one or two inputs on the dev kit)
- Some internal analog tracks crossing split power planes.
Testing:
I've setup code to trigger the 16 channel ADC cascade sequence off a timer interrupt at 5us intervals (i.e. sampling @ 200kHz), and the ADC ISR stores each of the results in external SRAM. The code takes 16384 samples from each channel, and then I perform a memory dump, load the data into Excel, and perform a 4096 point FFT on the first quarter of the samples and check the bitspread (minimum to maximum spike values).
I have tried changing a few things, including the ADC clock frequency and aqusition window, the sample rate (200kHz, 333kHz and 500kHz), the ADC channel sequencing (both channel count and channel order).
Results:
I'm getting (generally) 20-30 bits of error (min to max spike) on all channels, except for 15 and 16 because these channels grounded so we only see half the range.
Here are some representative images showing typical bit spread on all channels, and the plot from one the first channel (IU1):
Here is the FFT associated with the first 4096 bits of the first channel (x-axis is Hz, y-axis is bits):
The above FFT used samples taken at 200kHz, with ACQ_PS = 0 and ADCCLKPS = 0 (ADC Clock = 25MHz, ADC Sample and Hold Time = 1/25MHz = 40ns). A nice, clean spike is seen at 66.6667kHz.
Below I tried changing the halving the ADC Clock frequency (i.e. ADCCLKPS = 1, ADC Clock = 12.5MHz, ADC Sample and Hold Time = 1/12.5MHz = 80ns) and the noise is now dispersed throughout the spectrum, with a major spikes at 33.333kHz, 83.333kHz and 50kHz:
Next I changed the ADC clock back to 25MHz, but tried sampling with a timer @ 6us (166.66kHz), and the noise spike shifted to 55.556kHz:
Can anyone suggest why I'm seeing different noise profiles depending on setup?
Could the noise be caused by the DSP/ADC, or be an artifact of the FFT process? Could the noise be a much higher frequency signal and my sampling rate is causing aliasing?
Does anyone have any information that would be helpful, or suggestings for further testing?
