Hello TI Community!
I am working with the TMS320F28335's SCI-A serial communication. When RXRDY/BRKDT interrupt is enabled by setting the RX/BKINTENA bit and desabling SCIFFENA the RXRDY/BRKDT interrupts (as well as the flags itselves have been tested) does not work. I assumed that the Pie configuration is ok, once that when enabled the FIFO Interrupt works fine.
Configuration that FIFO interrupt works:
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block
PieCtrlRegs.PIEIER9.bit.INTx1=1; // PIE Group 9, int1
IER = 0x100; // Enable CPU INT
EINT;
SciaRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback
// No parity,8 char bits,
// async mode, idle-line protocol
SciaRegs.SCICTL1.all =0x0003; // enable TX, RX, internal SCICLK,
// Disable RX ERR, SLEEP, TXWAKE
SciaRegs.SCICTL2.bit.TXINTENA =1;
SciaRegs.SCICTL2.bit.RXBKINTENA =1;
//SciaRegs.SCIHBAUD = 0x0000;
//SciaRegs.SCILBAUD = SCI_PRD;
SciaRegs.SCIHBAUD = 0x01;
SciaRegs.SCILBAUD = 0xE7;
//SciaRegs.SCICCR.bit.LOOPBKENA =1; // Enable loop back
SciaRegs.SCIFFTX.all=0xC028;
SciaRegs.SCIFFRX.all=0x0028;
SciaRegs.SCIFFRX.bit.RXFFIL = 0x0010;
SciaRegs.SCIFFTX.bit.SCIFFENA = 0;
SciaRegs.SCIFFCT.all=0x00;
SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset
SciaRegs.SCIFFTX.bit.TXFIFOXRESET=1;
SciaRegs.SCIFFRX.bit.RXFIFORESET=1;
When I want to use RXRDY/BRKDT interrupt I desable FIFO registers as well as FIFO interrupt, but RXRDY/BRKDT does not work yet. I followed the "scia_loopback_interrupts" example to do the configurations. It's funny how in this example both interrupts are set, both RXRDY/BRKDT and FIFO interrupt (TXFFINT), when it's clear for me in the SCI manual that only one of them can work at a time, once that the RXRDY/BRKDT interrupt only works with the FIFO desabled, as shown in "Figure 1-10. SCI FIFO Interrupt Flags and Enable Logic" of SPRUFZ5A.
Can anyone help me set the RXRDY/BRKDT interrupt? Or even make those flags work. I tested the flags using breakpoints but when data was sent none of them was detected.