BQ77PL900 False UV Detection

Unfortunately damage is not uncommon.  There should be several posts on different issues, none stand out to reference here.  If abs max is exceeded and damage occurs, the typical is some resistive path from an input to ground (single ended) or between inputs (differential).  You will normally be able to see this in the VIOUT reading.  Some possibilities or suggestions:

• If using less than 10 cells, be sure the CONFIG pins are connected firmly, otherwise the unused shorted cell input(s) will be used in comparison and show a permanent UV.
• Be sure any calibration routine in the MCU is not masking a cell voltage difference
• Check for firm connection of each cell to its terminal, a high resistance can allow the voltage to fluxuate when sampled by the device.  The MCU may filter differently than the UV detection and the device may report a UV while the MCU gives a filtered voltage which seems acceptable
• Check that the input filter resistors are installed as intended by the design and for the part.  They should be large enough to limit balance current to a safe level and small enough to avoid errors in measurement, 400 ohm typical up to 1k or perhaps more.

Bottom up connection is a typical recommendation, the differential capacitors push the upper cell connections up as each successive cell is connected.  This does technically violate abs max as the capacitor will (dis)charge and current flows through the body diode of the internal balance FETs.  Connecting bottom then top with the cell inputs defined between is another option.  Good ESD control in the handling of the components and assemblies of course is important.  How implementers avoid damage to the device varies, I don't know the popularity of each of these possibilities:

• Careful process control of assembly sequence
• Avoiding voltage on PACK during assembly which can wake the IC causing sampling and supply loads
• Avoiding ground loops between assembly equipment and fixture which might force a high differential voltage on cell inputs of the board
• Avoiding contact of fixture wires to the wrong cell connection during assembly
• Designing in zeners at the cell inputs.  This is an expense and and defect opportunity.  The zener is exposed to the cell voltage, and it does not specifically limit the voltage at the IC pins since there is a multi-input filter network.
• Designing in zeners at the IC pin inputs.  This is again an expense and a challenge to pick a value since the pin voltages will vary with balancing and there may be little margin for component tolerance between balancing voltage and abs max limits.
• Assembly fixture design which limits input voltage with zeners during assembly, but does not remain in the product.
• Assembly fixture design which distributes voltage or pre-biases the board inputs so there are no large differential voltages at connection, again removed from the product.  Some caution is needed here since a resistor divider which distributes voltages when properly connected can become a pull up or down which induces a differential voltage if it is not firmly connected.

Hope this is helpful.