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UCC256302: UCC256302 FB/BLK restart sequence and VCC capacitor question?

Bob Lee62837
Mastermind 7230 points
Part Number: UCC256302
Other Parts Discussed in Thread: UCC25630-1EVM-291

Dear support member,

My customer used UCC256302.

I have a question.


Q1.
Shut down FB pin with GND.
Would you teach me the restart sequence block?


Q2.
Shut down BLK pin with GND.
Would you teach me the restart sequence block?

Q3.
Qtot of equation 73 is described as 1.6 mC,
I think that the contents are QGH and QGL of the MOSFET.
Qtot = QGH + QGL

In equation 73, how many margins did you set?
2.2 μF is connected on the evaluation board (UCC25630-1EM-291).


Best regard.
Bob Lee.

  • 0
    TI__Mastermind 27145 points
    Hi Bob,

    Thanks for your interest in UCC256302. When FB pin is pulled to ground for more than 200ms, the controller enters the FAULT state. When FB is released, the controller transitions to JFETON. When VCC becomes larger than ~26V, the controller begins switching and performs a soft start.

    If BLK is pulled below BLKStopThreshold, the controller will behave in the same fashion as if FB was held low. The controller will go into the FAULT state, then JFETON, then soft start

    There is 2.2uF + 120uF connnected to VCC in the UCC25630-1EVM-291. I would suggest having a minimum of 100uF for VCC.

    Best Regards,
    Ben Lough
  • 0 in reply to Benjamin Lough
    Mastermind 7230 points

    Dear Benjamin Lough,


    Thank you very much for reply.

    May I ask add a question about VCC capacitor?

    Considering that PFC does not operate from RVCC,
    I think the gate charge of the MOSFET (QGH+QGL) is enough for the VCC capacitor.
    but is the content wrong?

    In that case, what is the capacity of the VCC capacitor?
    Is 2.2uF enough?

    Best regard.
    Bob Lee.

  • 0 in reply to Bob Lee62837
    TI__Mastermind 27145 points
    Hi Bob,

    VCC must have large enough capacitance to keep VCC above 10.5V during the burst-off period while in burst mode. I do not recommend sizing the VCC capacitance based on the MOSFET gate charge. In some cases, you can push VCC capacitance slightly lower than 100uF but this depends on how high the burst mode threshold is set. I would suggest planning to include at least 1 electrolytic capacitor in your layout for VCC.

    Best Regards,
    Ben Lough
  • 0 in reply to Benjamin Lough
    Mastermind 7230 points

    Dear Benjamin Lough,

    Thank you very much for reply.

    May I ask add a question about Fig 44 System states?

    We want to realize on / off by the external signal as customer's function.
    (System External Shut Down AND Start Up)

    Would you teach me about Fig44 System State?


    Q1.
    When the time of FBLessThanBMT exceeds 200 ms, timeout (13)
    Transition to "JFET OFF" state.

    What will the state transition from "JFET OFF"?


    Q2.
    What will the state transition from FBLessThanBMT time out?

    FBLessThanBMT I do not know the time out point?
    Because I want to know where to stand up.
    Because I want to know the loop when FBLessThanBMT continue.

    Best regard.
    Bob Lee.

  • 0 in reply to Bob Lee62837
    TI__Mastermind 27145 points

    Hi Bob,

    1. The controller will stay in JFET OFF state until the BLK pin is above the BLKStart threshold. Once the BLK pin voltage is greater than BLKStart, the controller transitions to the WAKEUP state to enable internal analog functions (~150us wait time). The controller then transitions to the CHARGE BOOT state when the LO signal is held high for an extended period of time in order to charge up the boot capacitor. Once the boot capacitor is charged, the controller will enter steady state run or light load run(burst mode).

    2. When the FB pin is held below the burst mode threshold for greater than 200ms, the controller will treat this as a fault. As long as FB is held below the burst mode threshold, the controller will not resume switching.

    Best Regards,

    Ben Lough

  • 0 in reply to Benjamin Lough
    Mastermind 7230 points

    Dear Benjamin Lough,

    Thank you very much for reply.

    I reply my customer your answer.
    I will feedback it.


    Best regard.
    Bob Lee.

  • 0 in reply to Bob Lee62837
    Mastermind 7230 points

    Dear Benjamin Lough,


    Thank you very much for reply.
    I feedback my customer situation.


    My customer plan production and mass production.
    There are multiple questions,
    as important request please answer.


    Q1.
    How much can the maximum resistance value go though the resistance value of the HV terminal is 5 KΩ?


    Q2.
    Could you teach the voltage characteristics of bulk voltage and LL terminal for burst threshold setting?


    Q3.
    Can the Fbreplica voltage be considered the same as the FB terminal voltage?


    Q4.
    Could you teach how to calculate Vthh and Vthl ?
    Also, do you do that with VCM calculating at 3V?

    Q5
    Could you teachl me the VCOMP transfer function at steady state ?
    (DS - P 16 Figure 26. Constants, resistors, etc. constants).

    Q6
    7.2.2.13 Design Considerations for Adaptive Dead-Time At which timing will the auto adjustment function turn ON and OFF?


    Q7
    Wakeup time is about 150 μs.
    Is there a margin (min , max)?


    Best regard.
    Bob Lee.

  • 0 in reply to Bob Lee62837
    TI__Mastermind 27145 points
    Hi Bob,

    1. The maximum current going through the HV resistors is when the startup circuit is charging the VCC capacitance. The startup current is 10.6mA typical.

    2. The burst mode is programmed at the LL/SS pin through a resistor divider. The voltage at the BLK pin is internally buffered to the LL/SS pin. This creates a difference in current in the top and bottom resistor in the LL/SS resistor divider. This difference in current goes into the LL/SS pin and is internally mirrored over an internal resistor. The resulting voltage creates the burst mode threshold. For reference, take a look at section 7.2.2.21

    3. FBreplica is the internally recreated feedback voltage signal from the opto-coupler current. FBreplica is the same as VCOMP. Yes, you can think of FBreplica as the feedback terminal voltage

    4. Vthh - Vtll is equal to VCOMP (FBreplica). VCM should always be 3.02V. Vthh and Vtll are always symmetric around VCM.

    5. The error amplifier will bias the opto coupler to sink a certain amount of current out of the FB pin. The opto-coupler current is taken from the internal current source IFB. The remaining current goes through an internal resistor RFB. The resulting voltage creates VCOMP (FBreplica). The relationship is VCOMP=RFB*(IFB-Iopto).

    6. The adaptive dead time circuit will turn on the next MOSFET when the controller has detected the switch node has finished slewing. Section 7.2.2.13 discusses how to ensure the controller will successfully detect the slew rate.

    7. I do not have specific margins on the wakeup time at the moment but I would expect very little variation in the wakeup time. This time is set by the internal state machine in the controller.

    Please let me know if there are any additional question I may help with.

    Best Regards,
    Ben Lough
  • 0 in reply to Benjamin Lough
    Mastermind 7230 points

    Dear Benjamin Lough,


    Thank you very much for reply.
    I appreciate it very much.

    I have a question from your answer.


    Q5 add question.
    VCOMP = VTH - VTL, but should this gain be considered as 1?


    Q6 add question.
    Does the gate turn on when the Dead-Time automatic adjustment function becomes 1 V / ns or less?
    Could you teach in the figure when it will gate turn on at what timing?


    Q7 add question
    Is there data on the design value or measured value of the wake-up time?


    Q14
    I want to know the values of VCC and RVCC voltages other than the data sheet.
    Data sheet description value
    VCC = 15 V: RVCC = 11.6 V, 12 V, 12.4 V
    VCC = 13 V: RVCC = 11.2 V, 11.8 V, 12.25 V


    I would like to know the following data,
    Could you teach?
    VCC = V: RVCC = 11.25
    VCC = V: RVCC = 9.75
    VCC = V: RVCC = 7.0


    Best regard.
    Bob Lee

  • 0 in reply to Bob Lee62837
    TI__Mastermind 27145 points

    Hi Bob,

    Q5: Yes, please consider gain as 1.

    Q6: The controller needs to sense a slew rate >1V/ns. Once the slew rate has fallen below 1V/ns, the controller considers the switch node to be "done slewing".

    Q7: The wakeup time is implemented as a 150us timer in the controller's state machine. I would need to talk to design if further detail is needed.

    Q14: My suggestion is to configure the bias winding to supply the VCC pin with a voltage >13V. Below 13V, the internal LDO used to generate the 12V rail does not have enough headroom and will likely cause the controller the cease switching from RVCCUVLO.

    Best Regards,

    Ben Lough

  • 0 in reply to Benjamin Lough
    Mastermind 7230 points

    Dear Benjamin Lough,

    Thank you very much for kindness answer.
    I appreciate it very much.

    I have a question from your answer.


    Q7 add question.
    About Wakeup time
    Do you need any information from my customer as detailed contents?


    Q14 add question.
    When bias windings are used, the charge from the bias windings can not be made in time.
    I am worried that starting and restarting will be repeated when the VCC restart voltage is 10.5 V or less.

    Is there something like this worry problem?
    Is there any countermeasure if this worry problem?


    Best regard.
    Bob Lee.

  • 0 in reply to Bob Lee62837
    TI__Mastermind 27145 points

    Hi Bob,

    Q7: Not at the moment. It will take a couple days for the design to to respond about the range of the wakeup time.

    Q14: The HV startup function will always charge the VCC node up to 26V before switching begins. This will put additional charge on the VCC capacitance to avoid VCC becoming too low during startup. The worst case condition is in burst mode when there is  long period where the controller does not switch. As long as there is enough capacitance on the VCC pin to hold VCC above 10.5V in burst mode, there should not be any issue with VCC becoming <10.5V.

    Best Regards,

    Ben Lough

  • 0 in reply to Benjamin Lough
    Mastermind 7230 points

    Dear Benjamin Lough,

    Thank you very much for answer.
    I will wait answer for a couple days.

    Best regard.
    Bob Lee.

  • 0 in reply to Bob Lee62837
    TI__Mastermind 27145 points
    Hi Bob,

    You can assume a tolerance of +/-10% on the wakeup time. Please note that this is from an internal digital clock so the wakeup time will be very accurate for the majority of devices.

    Best Regards,
    Ben Lough
  • 0 in reply to Benjamin Lough
    Mastermind 7230 points

    Dear Benjamin Lough,


    Thank you very much for answer.
    I reply my customer your answer.

    Also, if I have any question from my customer,
    please your support.


    Best regard.
    Bob Lee.

  • 0 in reply to Bob Lee62837
    Mastermind 7230 points

    Dear Benjamin Lough,


    Thank you very much for reply.
    I appreciate it very much.

    I have a question from your answer.


    Q14 add question.

    I think that it is an IC assuming that RVCC is connected to IC of PFC,
    If there is no relationship between the voltage of RVCC and Vcc, it is not possible to decide start / stop of PFC IC and design calculation can not be done.

    I would like to know the following data,
    Could you teach?
    VCC = V: RVCC = 11.25
    VCC = V: RVCC = 9.75
    VCC = V: RVCC = 7.0


    Q15.
    Although the audible noise countermeasures are described 6 Optimize the System for Audible Noise, in Application Report (SLUA836A),
    Is not there anything else countermeasures?

    Best regard.
    Bob Lee.

  • 0 in reply to Bob Lee62837
    TI__Mastermind 27145 points

    Hi Bob,

    Q14:

    If VCC=13V and a 100mA load is on the RVCC pin, RVCC will be ~11.5V at room temperature.

    If VCC=11.25V and a 100mA load is on the RVCC pin, RVCC will be ~9.8V at room temperature.

    UCC256302 will enable the HV startup function as soon as VCC drops to 10.5V.

    Q15:

    Shown below is an additional method for audible noise mitigation:

    During the burst on period, VFB_1 slowly increases and the current stolen from the internal FB current source, Is, slowly decreases. This circuit provides a soft on/off and also increases the burst packet size. By increasing the packet size, the burst packet frequency can be greatly reduced to further avoid the audible range.

    Best Regards,

    Ben Lough

  • 0 in reply to Benjamin Lough
    Mastermind 7230 points

    Dear Benjamin Lough,

    Thank you very much for your answer.
    I reply my customer your answer.

    I will feed back it.

    Best regard.
    Bob Lee.