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LM5116 Output Voltage Issue

Nick Velado
Prodigy 190 points
Other Parts Discussed in Thread: LM5116

Hi,

I have implemented an LM5516 to step our DC input down to 9V, using Webbench Designer with inputs of Vin min = 10V, Vin max = 55V, Iout = 3A.  Using the output design, with slightly different parts in certain cases, the output voltage of the regulator seems to be less than expected, with more than a 2V drop as the input voltage drops less than 11.5V.  Furthermore, seeing what appears to be an 800mV, 10ms drop in the regulator output every 100ms.  So, to summarize, here's the issue:

At 13Vin, .35A load current, Vout = 8.88V- Good

At 12Vin, .40A load current, Vout = 8.85V- OK

At 11Vin, .3A load current, Vout = 8.35V- Not good

At 10.5Vin, .1A load current, Vout = 8.1V- Not good

At 10Vin, 30mA load current, Vout = 8.5V- Not good

Expecting the overall voltage drop to be able to handle a 9V output even at 10V under full system load (~1.2A).

The components and measurements observed are as follows:

Vin on regulator tied to Vin

EN to 100k pull-up to Vin

UVLO to 40.2k/10k voltage divider to Vin--6V under voltage threshold.  At Vin=10V, UVLO voltage=2V, well above 1.2V threshold

RT/SYNC to 5.11k pull-down--525KHz frequency according to designer

Feedback through 9.1k/1.43k voltage divider from Vout

Using 12uH inductor- Wurth 744770112 5.9A

Using N-Fets Infineon BSC123N08NS3 55A 12.3mOhm

At 10Vin, seeing a .5V drop across the upper fet.

Trying to understand why the output voltage is so much lower than expected across working input voltages.  Also, a very low audible switching sound can be observed while the regulator is working.  Thanks,

Nick

  • 0
    TI__Intellectual 940 points

    Nick,

    The problem looks like the LM5116 is running out of duty cycle, especially at higher currents.  Looking at page 5 of the data sheet under PWM Comparators, there is a maximum forced off time of .58 us.  At the reported frequency of 525 kHz, the total period is 1.9us.  The duty cycle for VIN = 10 volts and VOUT = 9 volts is .9.  However the duty cycle is really higher than this due to losses in the MOSFETs, the DC loss in the inductor, and PCB wiring losses.  So the required duty cycle to maintain regulation will be somewhat greater than 90%. Using D = .9 as a best case, the required on time is .9 X 1.9 us = 1.71 us.  However, the forced off time is .58us, so the available on time is only 1.9us - .58 us or 1.31 us.  So by this analysis, the LM5116 is hitting a duty cycle stop and cannot regulate the output voltage.  This will get worse at higher currents because of the losses referred to previously.  The best way out of this situation is to lower the frequency so that the period is longer.  The forced off time remains the same but is now a smaller percentage of the total period allowing larger duty cycles.  I would recommend lowering the frequency to 250 kHz as a first iteration.  If everything is ok, then increase the frequency until failure is noted.  This will give you a good idea of the maximum frequency possible with this design.  Also note I used the worst case forced off time in the datasheet.  Using the minimum value, this design is right on the edge.

    Refer to the LM118 datasheet for a discussion of forced off time vs maximum operating frequency.  The analysis applies equally to the LM5116 using the .58 us forced off time.

    Regards,

    Ron Crews

  • 0 in reply to Ronald Crews
    TI__Genius 15810 points

    Thanks Ron. We will investigate this on Webench.

    Regards,
    Akshay 

  • 0 in reply to Ronald Crews
    Prodigy 190 points

    Hi Ron,

    Thanks so much for the quick response!  You're right on the money, reducing the switching frequency cleared this issue right up.  Now, seeing about a .5V drop across the regulator, as expected.  Thanks!

    Nick

  • 0 in reply to Nick Velado
    TI__Expert 6365 points

    Hey Ron and Nick,

    I have made the change in Webench for the Toff setting. It allows for more margin for the actual design and reduced the max operating frequency at high duty cycle conditions..

    Regards

    Howard