Hi,
I have gone through various App notes on RF layout design from TI, Cypress and Atmel. I understand that each manufacturer recommends particular layout design for their chips. However, I'm designing a PCB which involves bluetooth chip and I have few silly questions. I'm using standard 4 layer stack. I also have no ground plane under antenna. I'm using balun to match the 50 ohm Impedance. I'm using standard 1 oz copper, dielectric of 4.4. However I'm confused in two things.
1. Trace width calculation from BLE chip's antenna pins to balun's differential pins. (Should I calculate trace width based on 100 ohm or 50 ohm impedance?)
2. Trace width from balun's single ended output to pcb trace antenna's feed point
3. I'm using Inverted F Antenna. How do I determine the trace width for IFA? (Calculate based on 50 ohm impedance?)
This questions are more of cross checking what I think should be the design. However I'm really confused in question 1.
I havent came across any TI's note which discuss the trace width and layer stack. IF there are any, please advise.
