Other Parts Discussed in Thread: ADS54J54,
Hi,
I am planning to use an ADC from TI with part number ADS54J54 interfaced to an Xilinx Virtex Ultrascale+ FPGA. This ADC has an JESD204B interface to the FPGA and wanted to know weather the TI-JESD204-IP core will be provided for interface validation.
Also wanted to know what are the limitations of usage of this IP. Would there be possibility to change certain parameters in the IP core to suit our application. Is there any cost involved for this IP core.
We are currently building proto type boards (2-4Nos) with one ADC on each board. We expect to get into production by early 2024 (50-100 Nos per annum) . This is for an data acquisition system we are building in house for Thales India
Thanks & Regards,
Rakesh Rajdev
Thales India Pvt Ltd
Ph - +919844108624