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TI-JESD204-IP: Require more Information on TI-JESD204-IP Core

Part Number: TI-JESD204-IP
Other Parts Discussed in Thread: ADS54J54,

Hi,

I am planning to use an ADC from TI with part number ADS54J54 interfaced to an Xilinx Virtex Ultrascale+ FPGA. This ADC has an JESD204B interface to the FPGA and wanted to know weather the TI-JESD204-IP core will be provided for interface validation.

Also wanted to know what are the limitations of usage of this IP. Would there be possibility to change certain parameters in the IP core to suit our application. Is there any cost involved for this IP core.

We are currently building proto type boards (2-4Nos) with one ADC on each board. We expect to get into production by early 2024 (50-100 Nos per annum) . This is for an data acquisition system we are building in house for Thales India

Thanks & Regards,

Rakesh Rajdev

Thales India Pvt Ltd

Ph - +919844108624

  • Hi Rakesh,

    The TI JESD IP is provided free of charge. There are a some use license restrictions, primarily that the same FPGA should not connect to any non TI JESD based data converters.

    The IP supports all Xilinx Ultrascale and 7000 series FPGAs and can be parameterized to match the LMFS mode and JESD link parameters of any data converter from TI. 

    Regards,

    Ameet

  • Hi Ameet,

    Thank you for your response. In which format will the IP core be provided, will this be a Netlist or will the source code etc be shared?

    Will there be any licensing required for production version of the boards using this IP (will have the same TI ADC and FPGA using in prototype)?

    Regards,

    Rakesh

  • Hi Rakesh,

    The core is provided as an encrypted system verilog file. The reference design files (part of the design around the core) will be non-encrypted system verilog RTL.

    Beyond TI device use restriction, there is no licensing requirement for production versions of boards that contain FPGAs with this IP.

    Regards,

    Ameet