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TI-JESD204-IP: TI-JESD204-IP Clock Configuration

Seongtaek Cho
Prodigy 105 points
Part Number: TI-JESD204-IP
Other Parts Discussed in Thread: ADS54J40, , LMK04828

TI-JESD204c-IP_Clock_Config.pdf

Hello,

I have a question about clock configuration of ADS54J40 and TI-JESD204-IP.

Please refer to the attached pdf file.

1. How many MHz clock should I put in the ADS54J40's SYSREF?  The sampling frequency of the ADC is 1Gsps and the line rate is 5Gbps when configuring 8 lanes.

2. How many MHz should I put in the refclk of the TI-JESD204C-IP?  When I input the line rate as 5Gbps in the transceivers wizard, 62.5MHz is selected as the default for the actual reference clock. 

   However, DCLK of LMK04828 could not make 62.5MHz.

3. How many MHz should I put in the sysref of the TI-JESD204C-IP? 

4. How many MHz should I put in the sys_clk of the TI-JESD204C-IP?  sys_clk seems to be used to create freerun_clk on TI-204C-IP.  Can I select 62.5MHz as the DRP clock in the transceivers wizard?

Regards

Cho

  • 0
    TI__Guru* 91947 points

    Cho,

    1. SYSREF = sample rate / (K * N) where N is any whole integer. Assuming you are using the ADC with K = 16, with N = 1, the max SYSREF clock you can use is 62.5MHz. With a large value of N, you can lower this frequency if desired.

    2. FPGA REFCLK is normally lane rate /80 = 62.5MHz, but I think it can be lower if needed. Another engineer will verify this.

    3. Same answer as number 1.

    4. Another engineer will answer this.

    Regards,

    Jim

  • 0 in reply to jim s
    TI__Mastermind 18011 points

    Hi Cho,

    2. For the GTX clock to the FPGA transceiver the clock should be the exact frequency that is chosen in the Vivado transceiver wizard. If you cannot use 62.5MHz then you can use 125MHz if this is available in the drop down menu in the transceiver wizard. 

    4.  The sys_clk has a requirement that it must be equal to or greater than LaneRate/80.

    For more information on the clocks be see section 6.4 of the TI204c IP User's Guide.

    Regards,

    David Chaparro 

  • 0 in reply to jim s
    Prodigy 105 points

    2262.TI-JESD204c-IP_Clock_Config.pdf

    Hello, 

    In TI-JESD204-IP, the default K=32. 

    When LMFS=8224 of ADS54J40, is N=8 correct?

    Then, is the sysref frequency 1000MHz(32*8) = 3.90625MHz?

    And looking at the datasheet, I'm not sure what the K stands for. Could you explain K?

    Regards,

    Cho

  • 0 in reply to Seongtaek Cho
    TI__Mastermind 23870 points

    Hi Cho,

    Relating to JESD, N refers to the converter resolution, in this case, for the AD54J40 in LMFS=8224 mode, the converter resolution is 14-bit, so N=14. K is a JESD parameter which determines the number of frames in a multi-frame boundary for 8b/10b encoding modes. In LMFS=8224 mode, the LMFC (local multi-frame clock) frequency shall be (fs/4)/K as mentioned in section 8.3.3 SYSREF Signal of the datasheet. Once this LMFC frequency is known, simply divide by any sub-harmonic of the LMFC. This is done by dividing the LMFC by a factor of 2^M, where M is any integer value. This ensures the SYSREF period will be aligned to a multi-frame boundary. Please see the image below.

    Regards, Chase