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Original question:

TI-JESD204-IP: JESD204C IP Core Integration Issue in Vivado for ZC706

TI-JESD204-IP: Using with an existing Artix-7 FPGA design

Taylor Niver
Prodigy 10 points
Part Number: TI-JESD204-IP
Other Parts Discussed in Thread: ADC31JB68,

Tool/software:

I'm trying to get the TI-JESD204-IP working on an Artix-7 (xc7a100tfgg484-2) to communicate with the TI ADC ADC31JB68. 

I'm getting a little confused on how to get the initial project set up.  Reading the TI204C-IP-Users-Guide.pdf it recommends first loading the reference design zc706_8b10b  for the Artix-7 and then following the directions below. I've add in my comments (in RED) for where I'm getting confused

  • Open the transceiver wizard and note down all the settings on all the pages of the wizard. This will be important in step <4> below, because the same settings will need to be created for the transceiver on the new FPGA : The zc706 design is a GTX transiever running at 6.25 Gbps and the Artix-7 (that I'm using) is a GTP 3.125 Gbps. It does not seem like copying those settings would make sense but there does not seem to be an actual Artix-7 reference design to copy the files from. How do I handle this part? I tried to look a the mgt_8b10b_wrap (gtx_8b19b_rxtx.sv) to see if I could reverse engineer what I needed to provide it but its pretty complicated with many wires. Also it supports TX and RX and I only need RX. 
  • Save the original tested project as a new project with the new FPGA / DevKit set as the target device/board. Choose the option to copy all the source files, IPs and constraints.
    Is this really the only way to add in the TI_JESD_IP? I already have an existing design and would really just prefer to import the TI_JESD_IP into it and instantiate it and mostly that seems pretty simple but the part that I'm not sure how to do is the mgt_8b10b_wrap, how do I get that one for just an Artix-7 with RX support only?

Thanks in advance for any help!

  • 0
    Prodigy 10 points

    Searching/looking through all of the reference designs, there is NOT one that even uses the gtp so there is not one that is a good example to base the mgt_8b10b_wrap off of for the Artix-7.  I'm attempting to use the zc706_8b10 per the documentation and manually modify the mgt_8b10b to reflect that of what the Artix-7 should use but I'm concerned when I change things in it I *could* break something needed by the encrypted portions of the TI-JESD204-IP so any help on this would be greatly appreciated.

  • 0 in reply to Taylor Niver
    Prodigy 10 points

    I've reached a point where now I'm just getting the following error:

    So something in my modified wrapper is incorrect and because of the encryption there is no way for me to debug it further. Please advise on how I get a working mgt_8b_10b_wrap for the Artix-7 using it's gtp. The manual does say this part is supported but, again, there is no working example to base a design from.

  • 0 in reply to Taylor Niver
    Prodigy 10 points

    I wanted to clarify that the reason I had to modify the mgt_8b10b_wrap and *could* not use it as is with the Artix-7 is mainly because there are some significant differences in the Artix-7 GTP transceiver wizard output verses the GTX transceiver wizard used in the zc706_8b10b ref example (with all settings matched between them), some examples of the differences are as follows:

    • Uses PLL instead of QPLL. This requires quite a bit of modifications to the wrapper file including some of the output signals
    • 8 gtx pairs generated instead of just one gtp by the Artix-7
       Example: There are entries for gt[X]_gtxrxp_in from gt0_gtxrxp_in through gt7_gtxrxp_in in the mgt_8b10b_wrap but the Artix-7 transceiver wizard only creates entries for gt0. There are many other signals like this since the zc706 reference design seems to have 8 GTX interfaces supported in it while the Artix-7 is only generating one gtp.

    Those are the biggest two differences but there were other naming changes and some other missing signals not generated by the Artix-7 transceiver wizard.