TDA4AEN-Q1: How to calculate performance for each R5-Core?

Hi,

Gibbs Shih said:

I feel confuse, how to calculate total 10K DMIPS?

Could please refer this https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1430962/tda4vh-q1-unexpected-result-in-dmips-test/5489043?tisearch=e2e-sitesearch&keymatch=Dhrystone%25252520testing%25252520tda4en#5489043  thread let us know if this helps.

Regards,

Karthik

Hi, Karthik

After reading this reference, I still feel confuse.

Base on our "promote slides", we claim 4x A53 have 18K DMIPS, and 3x R5 have 10K DMIPS.

So I try to understand how to "correct" calculate "DMIPs" in Our SoC.

And this question was feedback from customer.

Question 1 : 

For example, ref. performance guide.

This is Dhrystone test result

4x A53 ->  2.8 x 1400 x 4 = 15680 DMIPS = 15.680 KDMIPS (VDD Core 0.85V)

Why we lost 2.32 KDMIPS? (18K-15.68K)

https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-j722s/10_01_00_04/exports/docs/devices/J7_Family/linux/Release_Specific_Performance_Guide.html?highlight=performance

Question 2 :

Do we have document to tell us  "dhrystone_per_mhz (DMIPS/MHz)" for TDA4AEN R5 Core?

Thank You.

Gibbs 

Hi, Karthik

Waiting your replies.

Any idea?

Thanks

Gibbs

Hello Gibbs,

I was asked to review this question.

#1 Regarding the 3-single-R5Fs running at 800MHz, I agree that the 10K number seems too high for a measured dhrystone.  I would guess its an estimate or a typo-error in the picture you provided.  Where did you get that 10K number from?  I did not see it on the TI website. The number can be clarified or corrected if you provide the source pointer.

I have run on the R5 on J7AEN and the best number I measured for dhrystone using inlining is 2.108.   Other TDA4 family SOCs are using 2K per core @1GHz based on a different compilers run.  So for a TDA4VH, there are 8 R5's each at 1GHz to give 16K in split mode (8x2DMIPS=16K total).   For J7AEN a number in the range of 2.1DMIPS/MHz x .8 x 3 cores = 5K.

#2 Regarding the A53, with inlining I believe someone measured a 3.3 with one tool chain to give the 18k (1.4x3.3x4).  With GCC I have seen ~3 when running. The SDK web report which you cite received a 2.8 is what that version of the SDK (env + compiler + libs) got in a given release.  That SDK number could be improved using a different tool chain version and environment.  The marketing numbers tend to publish the best someone can do for a core where the SDK publishes what it achieved without special effort.

While dhrystone is a common metric, its a pretty weak indicator for Cortex-A core as its a in-L1 cache benchmark.  When predicting performance many benchmarks should be used together... or better yet your own application is the best target.

Hi, Richard

Thanks your replies.

About question 1, for you reference.

If something wrong, we way need to modify this slides.

https://texasinstruments.seismic.com/app#/doccenter/54ea9a21-3b61-4aa8-9181-5c52fc7abd84/doc/%252Fddf710f049-ddb3-5185-ecae-6367e1cb5c1c%252FdfOTIxZjUwNjUtZDE0Yi00YTA0LWFjNTMtZDI5ODhkMDI1ODNk%252CPT0%253D%252CSkFDSU5UTw%253D%253D%252Flfec91780c-0fff-4005-b89f-61aaa251cc21//?mode=view&parentPath=sessionStorage

--> p10,

Gibbs