I regularly respond to questions on the attempting to clarify misunderstanding of differences between the specified and operating conditions used in our product datasheet (PDS) for defining various op amp parameters. These differences have great technical implications since PDS limits apply only to specified ranges. Therefore, it is paramount for designers not to use operating conditions as a guide for their board design because this may directly lead to system underperformance or outright failure.
One common issue with op amps occurs when the system designer inadvertedly exceeds the specified input common-mode voltage range. While reviewing the simplified topology of the bipolar differential input pair in Figure 1, it is clear that the linear range on the upper side of the supply voltage extends only to within a total voltage of Vsat of Q1 and Vbe of Q2. This means the input common-mode non-linearity begins around 1V below positive rail and becomes worse as the input voltage gets closer to the positive rail, +Vs. Driving IN+ any closer to positive rail results in a decrease of the current biasing the input differential pair. This condition may not cause an increase in the input voltage offset but it will surely result in lowering the op amp’s bandwidth (gm~Itail/Vt) and slew rate (SR~Itail/Cc), as well as increasing the input voltage noise (Vnoise~1/Itail) greatly diminishing the op amp’s AC performance.
Classic Input Stage
Similarly, on the lower side of the input common-mode voltage range, driving the IN+ within Vsat of negative supply, or within ~300mV above (-Vs) @25C, would cause the loss of the transistor’s DC gain (β->1). This would lead to a sudden increase in the input bias current and much higher input current noise (Inoise~2*q*IB).
When it comes to the op amp’s output stage, a given circuit topology determines the range of the output voltage swing. In the case of common-emitter configuration shown in Figure 2, the linear output swing from positive rail is limited by the Vbe of Q1 and Vsat of Q2 resulting in Vout < [(V+)-1V]. The same type of analysis for the low side of output voltage swing, results in Vout>[(V-)+1V].
In case of the common-collector (bipolar), or common-drain (CMOS), output configurations shown in Figure 3, the linear output swing from the rails is only limited by Vsat of the output transistors, which is a function of the output current, Iout. Therefore, [(V-)+Vsat] < Vout < [(V+)-Vsat].
The change in Vsat with the change in Iout is shown in Figure 4 where higher output current results in higher Vsat and leads to a decrease of the output voltage swing.
The main distinction between different voltage output swing ranges has to do with how it is exactly defined within the datasheet specified parameter (see Figure 5 below). The voltage output swing from the rail refers to a non-linear operating condition of the output stage where output transistors are fully saturated. Under such conditions, the output will swing closer to the rails, but its performance will be significantly compromised by much higher Vos, lower open-loop gain (AOL) and greatly diminished AC performance.
On the other hand, the conditions used in specifying AOL call for the output voltage to swing further away from either rail, allowing the output transistors to operate in the linear region. Doing so results in much lower Vos, higher AOL and AC performance that meets all PDS specified limits.
In summary, the system designers should adhere to product datasheet specified, and not operating, ranges in order to take full advantage of the op amp’s true performance capabilities. It is especially important to use the amplifier within its specified input voltage range, as defined in the condition column for the CMRR specification since failure to do so may profoundly affect the op amp’s AC performance. When it comes to the output voltage range, in order to assure linear operation, users must follow the conditions defined in AOL specification.
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