Linux/DRA722: dra722/dra725

samgyung zhang

Part Number: DRA722
Other Parts Discussed in Thread: DRA72

Tool/software: Linux

Hi,i met a problem.My project required to support two lcd displays,both of their resolution is 1920*720.Is that dra722 or dra725 is capale to display two lcds(1920*720) simultaneously?Can you give me some schemes or advise?My project is work on sdk7.04.00.03,kernel 3.14!Hope to get your respond soon.Thanks very much!

Regards,
samgyung

over 8 years ago

0 Yordan Kamenov over 8 years ago

TI__Mastermind 42515 points

Hi Samgyung,

In this thread you seem to have both LCDs running:
e2e.ti.com/.../583789

Can you give some more details what went wrong?

Regards,
Yordan

0 samgyung zhang over 8 years ago in reply to Yordan Kamenov

Expert 1060 points

hi，Yordan Kamenov

Sorry for late respond! Indeed, i did have both LCDs running.Everything run well if both LCDS' pixelclock is low.If the lower pixelclock is set,it means that the LCDs have lower FPS .I have tested on two LCDS,both LCDS' resolution is 1280*720.If one LCD is set to 51 FPS,that the other LCD is only able to set to 14FPS.If i enhace the pixelclock of that LCD,that something unexpected happen,that LCD went black,as the weston would printf some error like that "no available mode for ".

What's more,the both LCDS can be set to about 30FPS,and that seem no problem too.

Some questions that i want to ask you is on the following:

1、Is there any limitation on LCDS' pixelclock while running dual display?What is that limitation?

2、I have a project that its' both LCDS required the resolution of 1920*720. In fact,i have not got the board of that project ,so i have not tested that if there any problem while running two lcds of 1920*720 .And the project require the FPS of one lcd is at least 50FPS,and the other lcd is at least 30FPS.I am not sure if

the dra722/dra725 is capable to complete that task.

Thans for your reading,hold to get your respond soon!

0 Yordan Kamenov over 8 years ago in reply to samgyung zhang

TI__Mastermind 42515 points

Hi Samgyung,

I have forwarded your question to DSS expert.

Regards,
Yordan

0 Venkat Mandela over 8 years ago in reply to Yordan Kamenov

TI__Expert 5970 points

Hi Samgyung,

I do not expect any issues with 2 1920x720 LCD's. On DRA722, I have tested two displays running at 60fps using kmstest. One of the displays is a 1920x1200 LCD and the other is a 1920x1080 HDMI monitor.

processors.wiki.ti.com/.../Processor_SDK_Linux_Automotive_Display_FAQ

Even if you do not have a board with two LCD's, you can create a fake LCD connector in the device tree and test with it.

processors.wiki.ti.com/.../Processor_SDK_Linux_Automotive_Display_FAQ

Also note that our latest release is based on K4.4. We can address issues from an SOC perspective but cannot support development on K3.14.

regards,
Venkat

0 samgyung zhang over 8 years ago in reply to Venkat Mandela

Expert 1060 points

Hi,Venkat Mandela
Is that means dra722 /dra725 can not support 2 1920x720 LCD's? How about 2 1280*720 LCDs?It seems that the FPS of two 1280*720 LCDs is a little low.I have use some patches from you to support dual display on kernel 3.14,thank for your great job.However,in fact ,i was confused some code in dpi.c,as you can see the details on the following:

static struct pll_data *dpi_get_pll_data(enum omap_channel channel)
{

/* IGNORE */

case OMAPDSS_VER_DRA72xx:
  switch (channel) {
  case OMAP_DSS_CHANNEL_LCD:
  case OMAP_DSS_CHANNEL_LCD3:
   dss_ctrl_pll_set_control_mux(0, channel);
   return dss_dpll_get_pll_data(0);
  case OMAP_DSS_CHANNEL_LCD2:
   dss_ctrl_pll_set_control_mux(1, channel);
   return dss_dpll_get_pll_data(1);//.In your code,two lcds that you parameter to 0 to select DPLL_VIDEO1.However,if i parameter to 0 for two lcds,something unexpected happened,the system corrupted,product some error like "kernel panic".So i parameter to 0 for lcd1,but parameter to 1 for lcd2,as you know,the dra722 only have one DPLL_VIDEO1,have no DPLL_VIDEO2.Parameter to 1 means that it would set CTRL_CORE_DSS_PLL_CONTROL[4:5] to select "RESEVE"?But it work,everything seems is ok expect low FPS.So i am worrying if it is a problem that lead to low FSP of the lcds.
default:
   return NULL;

/* IGNORE */

}

0 Venkat Mandela over 8 years ago in reply to samgyung zhang

TI__Expert 5970 points

Hi,

Can you use dss_clockdumps.sh script described below to check the PLL output clock rate?

processors.wiki.ti.com/.../Processor_SDK_Linux_Automotive_Display_FAQ

What is the user space API your application is using? If you application uses only one display, are you able to hit 60 fps?

regards,
Venkat

0 samgyung zhang over 8 years ago in reply to Venkat Mandela

Expert 1060 points

hi,venkat,

I have run dss_clockdumps.sh to understand DSS,finally i found the clock like that "DPLL_VIDEO1→DSI1_A_CLK→LCD1，DSS clk→LCD2“。As you can see the detail from the dum_dss.txt in the attatchment.On the other hand,we are using the weston with ivi-shell.If there is only one lcd,setting to 60fps is ok.If there is two LCDs,the weston would product some trace like the following:

"Output Unknown-1, (connector 4, crtc 10)
12279.10>                mode 1280x720@13.1, preferred, current
12279.10>                mode 1280x720@13.1, preferred
12279.10> [08:00:03.998] Chosen EGL config details:
12279.10>                RGBA bits: 8 8 8 8
12279.10>                swap interval range: 1 - 1
12279.10> [08:00:03.998] Failed to initialize backlight
12279.10> [08:00[    4.204799] OS:MSG:g5_get_bclk:rate=16000Hz
12279.10> :03.998] Output Unknown-2, (connector 16, crtc 18)
12279.10>                mode 1280x720@51.6, preferred, current
12279.10>                mode 1280x720@52.4, preferred

Fullscreen dum_dss.txt Download

root@dra7xx-g5-r1:/media/usbstorage0# ./dss_clockdumps.sh
12437.00> 
12437.00> 
12437.00> =====================DSS clock script===================
12437.00> Dumps internal clocks and muxes of DSS
12437.00> 
12437.05> CTRL_CORE_DSS_PLL_CONTROL (0x4a002538) = 0x000002A6
12437.07> video1 PLL :  Enabled
12437.08> video2 PLL :  Disabled
12437.10> HDMI   PLL :  Disabled
12437.11> DSI1_A_CLK mux : DPLL Video1
12437.13> DSI1_B_CLK mux : DPLL video2
12437.16> DSI1_C_CLK mux : DPLL Video2
12437.16> 
12437.18> DSS_CTRL (0x58000040) = 0x00010001
12437.19>  2: LCD1 clk switch :  DSI1_A_CLK
12437.21>  3: LCD2 clk switch :  DSS clk
12437.22> 10: LCD3 clk switch :  DSS clk
12437.24>  1: func clk switch :  DSS clk
12437.25> 13: DPI1 output     :  LCD1
12437.25> 
12437.30> ========================================================
12437.36> Register dump for DPLL video1
12437.36> |----------------------------|
12437.36> | Address (hex) | Data (hex) |
12437.36> |----------------------------|
12437.36> | 0x58004300    | 0x00000018 |
12437.36> | 0x58004304    | 0x00002683 |
12437.36> | 0x58004308    | 0x00000000 |
12437.36> | 0x5800430C    | 0x00000600 |
12437.38> | 0x58004310    | 0x00E16008 |
12437.38> | 0x58004314    | 0x00000000 |
12437.38> | 0x58004318    | 0x00000000 |
12437.38> | 0x5800431C    | 0x00000000 |
12437.38> | 0x58004320    | 0x00000000 |
12437.38> |----------------------------|
12437.38> 
12437.38> Details for DPLL video1
12437.44> PLL status  :  Locked
12437.44> M4 hsdiv(1) :  Active
12437.44> M5 hsdiv(2) :  inactive
12437.44> M6 hsdiv(3) :  Active
12437.44> M7 hsdiv(4) :  inactive
12437.44> 
12437.71> PLL_REGM =  3
12437.72> PLL_REGN =  0
12437.72> M4 DIV   =  0
12437.72> M6 DIV   =  0
12437.72> M7 DIV   =  0
12437.72> 
12437.72> Clock calculations (DPLL video1)
12437.72> sysclk = 20000000
12437.72> DCO clk = sysclk * 2 * REGM / (REGN + 1) = 120000000
12437.72> M4clk (clkcout1) = DCO clk / (M4 DIV + 1) = 120000000
12437.72> M6clk (clkcout1) = DCO clk / (M6 DIV + 1) = 120000000
12437.72> M7clk (clkcout1) = DCO clk / (M7 DIV + 1) = 0
12437.72> 
12437.80> ========================================================
12437.80> Clock O/P of MUXes
12437.82> Error: I2C Read failed
12437.83> Error: I2C Read failed
12437.83> Error: I2C Read failed
12437.92> DSI1_A_CLK :  120000000
12437.92> DSI1_B_CLK :  0
12437.92> DSI1_C_CLK :  0
12437.92> 
12438.00>  2: LCD1 clk :  120000000
12438.02>  3: LCD2 clk :  59000000
12438.02> 10: LCD3 clk :  59000000
12438.02>  1: func clk :  59000000
12438.02> 
12438.33> LCD1 logic clk(/ 1 ) :  120000000  pix clk(/ 8 ) :  15000000
12438.33> LCD2 logic clk(/ 1 ) :  59000000  pix clk(/ 1 ) :  59000000
12438.35> LCD3 logic clk(/ 4 ) :  14750000  pix clk(/ 1 ) :  14750000
12438.35> 
12438.35> root@dra7xx-g5-r1:/media/usbstorage0#

0 Venkat Mandela over 8 years ago in reply to samgyung zhang

TI__Expert 5970 points

Samgyung,

If you use the below patches, LCD1 and LCD2 should have the same clock. Your clock dump shows different clocks for LCD1 and LCD2. Can you check the below patches on the EVM, verify the clock dumps and then check the porting to your hardware?

No. URL Headline
1 review.omapzoom.org/37626 omapdss: pll: fix writing M6 & M7 divs
2 review.omapzoom.org/37627 tmp:fix for VOUT1 + VOUT2 enablement to have LCD1 and LCD2
3 review.omapzoom.org/38278 HACK: Enable M4 and M6 dividers always.
4 review.omapzoom.org/38279 dra72: dts: enable vout2

regards,
Venkat

0 samgyung zhang over 8 years ago in reply to Venkat Mandela

Expert 1060 points

Hi,venkat,

I have used your patches long time ago,the only difference between your patches and my code is in the function "dpi_get_pll_data" in linux/driver/video/fbdev/omap2/dss/dpi.c,as you can see the detail in the following,after you read the code,you will understand why the clock of LCD2 is different

from LCD1.

YOUR CODE

static struct pll_data *dpi_get_pll_data(enum omap_channel channel)
{

/***************************************************/

case OMAPDSS_VER_DRA72xx:
  switch (channel) {
  case OMAP_DSS_CHANNEL_LCD:
  case OMAP_DSS_CHANNEL_LCD2:
  case OMAP_DSS_CHANNEL_LCD3:
   dss_ctrl_pll_set_control_mux(0, channel);
   return dss_dpll_get_pll_data(0);
  default:
   return NULL;
}

MY CODE

static struct pll_data *dpi_get_pll_data(enum omap_channel channel)
{

/***************************************************/

case OMAPDSS_VER_DRA72xx:
  switch (channel) {
  case OMAP_DSS_CHANNEL_LCD:
  case OMAP_DSS_CHANNEL_LCD3:
   dss_ctrl_pll_set_control_mux(0, channel);
   return dss_dpll_get_pll_data(0);

case OMAP_DSS_CHANNEL_LCD2:

dss_ctrl_pll_set_control_mux(1, channel);
return dss_dpll_get_pll_data(1);

default:
return NULL;
}

The reason why i make difference is that it would product some error seriouly if i used your patches totally.I have put the log in the attachment,it indicated that some errors like that "PC is at pll_get_hsdiv_rate+0x2/0x8 LR is at dispc_mgr_lclk_rate+0x9b/0xa0".As you can see the detail in the attachment.

Fullscreen 2235.log.txt Download

   31.48: |--- Mark:01 --- COM-Error --- Date: 18.08.2017 --- Time: 14:00:56.39 ---|
   32.10> 
   32.13> U-Boot SPL 2014.07-00119-g07486c5 (Aug 17 2017 - 19:57:51)
   32.13> DRA722-GP ES2.0
   32.13> platform:g5 demoBoard identified, using 0 entries B(48) C(48)
   32.15> Get: magic=0x81488148 flag=0x001f0001
   32.32> MBR is match, no upgrade!
   32.41> 
   32.41>  starting kernel ...
   33.57> [    0.000000] GIC CPU mask not found - kernel will fail to boot.
   33.57> [    0.000000] GIC CPU mask not found - kernel will fail to boot.
   33.57> [    0.023336] /cpus/cpu@0 missing clock-frequency property
   33.61> [    0.661647] omap-dwc3 48880000.omap_dwc3_1: unable to get extcon device : extcon_usb1
   33.64> [    0.679965] omap_voltdm 4a0025cc.voltdm: Unable to get vdd regulator:-517
   33.64> [    0.686798] coproc iva_coproc: coproc clock notifier not ready, retry
   33.64> [    0.694422] omap_voltdm 4a0025e0.voltdm: Unable to get vdd regulator:-517
   33.64> [    0.701287] coproc dsp_coproc: coproc clock notifier not ready, retry
   33.71> [    0.764589] omap-sham 4b101000.sham: initialization failed.
   33.72> [    0.790913] ZSY device->name=omapdrm
   33.89> [    0.809706] ZSYchannel=0
   33.89> [    0.870788] ZSYchannel=2
   33.96> [    0.958318] pinctrl-single 4a003400.pinmux: pin 4a003824.0 already requested by 4a003400.pinmux; cannot claim for 0-0058
   33.96> [    0.969301] pinctrl-single 4a003400.pinmux: pin-265 (0-0058) status -22
   33.96> [    0.975948] pinctrl-single 4a003400.pinmux: could not request pin 265 (4a003824.0) from group tps65917_pins_default  on device pinctrl-single
   33.96> [    0.988728] palmas 0-0058: Error applying setting, reverse things back
   33.96> [    0.997672] prom_parse: Bad cell count for /ocp/i2c@48070000/tps65917@58
   33.97> [    1.019196] prom_parse: Bad cell count for /ocp/i2c@48070000/tps65917@58
   34.78> [    1.837061] MAXIM_LVDS 2-0040: no powerdown_gpio two node
   35.20> [    2.252455] Rootfs is not in EMMC, init the deferred driver in advance
   35.39> Get: magic 0x81488148 flag 0x1f0001
   35.75> [    2.470417] Unable to handle kernel NULL pointer dereference at virtual address 00000020
   35.75> [    2.478592] pgd = c0004000
   35.75> [    2.481310] [00000020] *pgd=00000000
   35.75> [    2.484910] Internal error: Oops: 17 [#1] PREEMPT SMP THUMB2
   35.75> [    2.490591] Modules linked in:
   35.75> [    2.493667] CPU: 0 PID: 14 Comm: kworker/u2:1 Tainted: G        W    3.14.57 #7
   35.75> [    2.501017] Workqueue: omapdrm apply_worker
   35.75> [    2.505225] task: ec916c00 ti: ec93a000 task.ti: ec93a000
   35.75> [    2.510650] PC is at pll_get_hsdiv_rate+0x2/0x8
   35.75> [    2.515201] LR is at dispc_mgr_lclk_rate+0x9b/0xa0
   35.75> [    2.520012] pc : [<c01b027a>]    lr : [<c01aa027>]    psr: 00000033
   35.75> [    2.520012] sp : ec93bd20  ip : 00000000  fp : 00000000
   35.75> [    2.531538] r10: 00000001  r9 : 000000ff  r8 : 00000500
   35.75> [    2.536784] r7 : 00000000  r6 : 00000001  r5 : 00000001  r4 : c061371c
   35.75> [    2.543337] r3 : c06126bc  r2 : c0396aa0  r1 : 00000008  r0 : 00000000
   35.75> [    2.549893] Flags: nzcv  IRQs on  FIQs on  Mode SVC_32  ISA Thumb  Segment kernel
   35.75> [    2.557407] Control: 50c5387d  Table: 8313406a  DAC: 00000015
   35.75> [    2.563176] Process kworker/u2:1 (pid: 14, stack limit = 0xec93a240)
   35.75> [    2.569555] Stack: (0xec93bd20 to 0xec93c000)
   35.75> [    2.573933] bd20: 00010004 00000500 000002d0 c01aa05b 00000800 c01aa19d 00000500 000002d0
   35.75> [    2.582147] bd40: 00000500 000002d0 00000800 ec93bdcb ec93bdd0 ec93bdd4 00000000 00000001
   35.75> [    2.590360] bd60: 00000000 00000001 00000000 c006c031 00000001 00000004 00000000 00000500
   35.75> [    2.598573] bd80: 000002d0 000002d0 000002d0 00000000 7fa60000 00000001 00000800 0000003f
   35.75> [    2.606786] bda0: 00000000 00000000 00000000 00000000 00000000 000000ff 00000000 00000000
   35.75> [    2.614999] bdc0: 00000000 00000000 01916c48 ecfb7348 00000001 00000001 00000000 000002d0
   35.75> [    2.623211] bde0: 00000000 00000000 00000800 00000500 000000ff 00000000 00000000 c01ab699
   35.75> [    2.631423] be00: 00000800 00000000 00000000 00000500 000002d0 00000500 000002d0 00000800
   35.75> [    2.639635] be20: 00000000 00000000 00000000 00000000 000000ff 00000001 00000000 eca78354
   35.75> [    2.647849] be40: 00000000 c01fc98b 00000000 000002d0 eca85410 ec962800 00000001 ec962960
   35.75> [    2.656063] be60: 00000002 eca78000 00000001 c30dcc00 eca783e4 c01ef82f 00000000 00000000
   35.75> [    2.664275] be80: ec962960 ec962964 00000800 c0376553 00000000 00100100 ec96298c eca783ec
   35.75> [    2.672488] bea0: eca783e4 00200200 00000000 eca783f4 eca783e4 c01eefaf c04bc440 00000002
   35.75> [    2.680700] bec0: eca78000 ec962994 eca7800c c30dcc00 ec93bee0 ec91b200 eca783f4 ec803600
   35.75> [    2.688913] bee0: ec93a000 c309c600 00000006 00000000 ec803600 c0032cb5 00000000 eca783f4
   35.75> [    2.697126] bf00: c309c600 ec91b218 00000001 ec91b200 ec803614 ec91b218 ec93a000 ec93a000
   35.75> [    2.705339] bf20: 00000001 c05df46a ec803600 c0032f45 c0032e61 c0598300 c0598300 ec93a000
   35.75> [    2.713552] bf40: ec93bf58 00000000 ec91d080 ec91b200 c0032e61 00000000 00000000 00000000
   35.75> [    2.721764] bf60: 00000000 c0036c43 365bbdba 00000000 b69aa0fd ec91b200 00000000 00000000
   35.75> [    2.729978] bf80: ec93bf80 ec93bf80 00000000 00000000 ec93bf90 ec93bf90 ec93bfa0 ec91d080
   35.75> [    2.738191] bfa0: c0036bc1 00000000 00000000 c000cce5 00000000 00000000 00000000 00000000
   35.75> [    2.746402] bfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
   35.75> [    2.754614] bfe0: 00000000 00000000 00000000 00000000 00000013 00000000 1f216bd5 3ef08766
   35.75> [    2.762834] [<c01b027a>] (pll_get_hsdiv_rate) from [<c01aa027>] (dispc_mgr_lclk_rate+0x9b/0xa0)
   35.75> [    2.771575] [<c01aa027>] (dispc_mgr_lclk_rate) from [<c01aa05b>] (dispc_mgr_pclk_rate+0x2f/0x48)
   35.75> [    2.780402] [<c01aa05b>] (dispc_mgr_pclk_rate) from [<c01aa19d>] (dispc_ovl_setup_common+0x81/0x1410)
   35.75> [    2.789665] [<c01aa19d>] (dispc_ovl_setup_common) from [<c01ab699>] (dispc_ovl_setup+0x95/0x9c)
   35.75> [    2.798405] [<c01ab699>] (dispc_ovl_setup) from [<c01ef82f>] (omap_plane_pre_apply+0xcf/0x1a4)
   35.75> [    2.807061] [<c01ef82f>] (omap_plane_pre_apply) from [<c01eefaf>] (apply_worker+0xb7/0x15c)
   36.09> [    2.815454] [<c01eefaf>] (apply_worker) from [<c0032cb5>] (process_one_work+0xad/0x238)
   36.09> [    2.823497] [<c0032cb5>] (process_one_work) from [<c0032f45>] (worker_thread+0xe5/0x274)
   36.09> [    2.831628] [<c0032f45>] (worker_thread) from [<c0036c43>] (kthread+0x83/0x9c)
   36.09> [    2.838887] [<c0036c43>] (kthread) from [<c000cce5>] (ret_from_fork+0x11/0x2c)
   36.09> [    2.846143] Code: f0fb b993 bf00 3106 (f850) 0021 
   36.09> [    2.851353] ---[ end trace 71ceb00d040f19ee ]---
   36.09> [    2.856081] Unable to handle kernel paging request at virtual address ffffffec
   36.09> [    2.863332] pgd = c0004000
   36.09> [    2.866047] [ffffffec] *pgd=adfd6821, *pte=00000000, *ppte=00000000
   36.09> [    2.872366] Internal error: Oops: 17 [#2] PREEMPT SMP THUMB2
   36.09> [    2.878045] Modules linked in:
   36.09> [    2.881119] CPU: 0 PID: 14 Comm: kworker/u2:1 Tainted: G      D W    3.14.57 #7
   36.09> [    2.888468] task: ec916c00 ti: ec93a000 task.ti: ec93a000
   36.09> [    2.893890] PC is at kthread_data+0x4/0xc
   36.09> [    2.897917] LR is at wq_worker_sleeping+0x9/0x80
   36.09> [    2.902554] pc : [<c0036f00>]    lr : [<c0033825>]    psr: a00001b3
   36.09> [    2.902554] sp : ec93baf0  ip : 00000000  fp : ec916c00
   36.09> [    2.914080] r10: ec916e78  r9 : 00000000  r8 : c05a277c
   36.09> [    2.919325] r7 : ec93baf8  r6 : ec93a000  r5 : ec916c00  r4 : 00000000
   36.09> [    2.925878] r3 : 00000000  r2 : 0420806c  r1 : 00000000  r0 : ec916c00
   36.09> [    2.932433] Flags: NzCv  IRQs off  FIQs on  Mode SVC_32  ISA Thumb  Segment user
   36.09> [    2.939859] Control: 50c5387d  Table: 8313406a  DAC: 00000015
   36.09> [    2.945627] Process kworker/u2:1 (pid: 14, stack limit = 0xec93a240)
   36.09> [    2.952006] Stack: (0xec93baf0 to 0xec93c000)
   36.09> [    2.956381] bae0:                                     ecfb7300 c037467f ecfb6700 c0598300
   36.11> [    2.964595] bb00: c0598300 c0598300 ecfb6700 00000001 ec916bf8 ec916df4 ec916bf8 ec916df4
   36.11> [    2.972809] bb20: c01b027e ec8ea800 ec916c00 c0026c37 c01b027e ec93bb48 ec93a000 00000001
   36.11> [    2.981023] bb40: c049c9c8 ec916e3c ec93bb48 ec93bb48 0000000b c05dfac4 c05a5ce8 ec93a000
   36.11> [    2.989237] bb60: 00000113 0000000b c01b027e 00000002 c01b0282 c000efff ec93a240 0000000b
   36.11> [    2.997450] bb80: 00000008 ec93a000 00000000 00000004 66000000 20626630 33393962 30666220
   36.11> [    3.005662] bba0: 31332030 28203630 30353866 30302029 00203132 00000001 ec93a000 c03720b9
   36.11> [    3.013876] bbc0: c04a3a00 ec93bbe4 c0495f9c 00000020 00000017 00000000 ec93bcd8 00000020
   36.11> [    3.022089] bbe0: ec93bcd8 00000001 ec93a000 c0371b3b ec916c00 c0012901 00000001 c05e370b
   36.11> [    3.030303] bc00: c049e567 c049e567 00000005 00000017 c05a5f10 c05a5ea0 c00127c9 00000020
   36.11> [    3.038517] bc20: ec93bcd8 00000001 00000000 c00082fb 6c0a0100 ffff0006 6c0a0000 ec93bc78
   36.11> [    3.046731] bc40: c05e3704 00000000 c05e3704 00000001 c05ea6cc c05ea6dc 00000028 c0180a0d
   36.11> [    3.054943] bc60: 00000028 ec93bc78 c05e3f08 c05ea6cc 00000037 00000028 c05e3704 00000001
   36.11> [    3.063156] bc80: c05ea6cc c05e3713 00000000 c004ad1f 00000000 00000001 c05e31f0 c0376789
   36.11> [    3.071368] bca0: 00000000 c05b2e58 00000000 c004907f c05e31f0 c0376553 0000071e c01b027a
   36.11> [    3.079582] bcc0: 00000033 ffffffff ec93bd0c 00000500 000000ff c000f5f5 00000000 00000008
   36.11> [    3.087795] bce0: c0396aa0 c06126bc c061371c 00000001 00000001 00000000 00000500 000000ff
   36.11> [    3.096008] bd00: 00000001 00000000 00000000 ec93bd20 c01aa027 c01b027a 00000033 ffffffff
   36.11> [    3.104222] bd20: 00010004 00000500 000002d0 c01aa05b 00000800 c01aa19d 00000500 000002d0
   36.11> [    3.112435] bd40: 00000500 000002d0 00000800 ec93bdcb ec93bdd0 ec93bdd4 00000000 00000001
   36.11> [    3.120648] bd60: 00000000 00000001 00000000 c006c031 00000001 00000004 00000000 00000500
   36.11> [    3.128861] bd80: 000002d0 000002d0 000002d0 00000000 7fa60000 00000001 00000800 0000003f
   36.11> [    3.137073] bda0: 00000000 00000000 00000000 00000000 00000000 000000ff 00000000 00000000
   36.11> [    3.145286] bdc0: 00000000 00000000 01916c48 ecfb7348 00000001 00000001 00000000 000002d0
   36.11> [    3.153500] bde0: 00000000 00000000 00000800 00000500 000000ff 00000000 00000000 c01ab699
   36.27> [    3.161713] be00: 00000800 00000000 00000000 00000500 000002d0 00000500 000002d0 00000800
   36.27> [    3.169925] be20: 00000000 00000000 00000000 00000000 000000ff 00000001 00000000 eca78354
   36.27> [    3.178138] be40: 00000000 c01fc98b 00000000 000002d0 eca85410 ec962800 00000001 ec962960
   36.27> [    3.186352] be60: 00000002 eca78000 00000001 c30dcc00 eca783e4 c01ef82f 00000000 00000000
   36.27> [    3.194565] be80: ec962960 ec962964 00000800 c0376553 00000000 00100100 ec96298c eca783ec
   36.27> [    3.202779] bea0: eca783e4 00200200 00000000 eca783f4 eca783e4 c01eefaf c04bc440 00000002
   36.27> [    3.210991] bec0: eca78000 ec962994 eca7800c c30dcc00 ec93bee0 ec91b200 eca783f4 ec803600
   36.27> [    3.219205] bee0: ec93a000 c309c600 00000006 00000000 ec803600 c0032cb5 00000000 eca783f4
   36.27> [    3.227418] bf00: c309c600 ec91b218 00000001 ec91b200 ec803614 ec91b218 ec93a000 ec93a000
   36.27> [    3.235630] bf20: 00000001 c05df46a ec803600 c0032f45 c0032e61 c0598300 c0598300 ec93a000
   36.27> [    3.243843] bf40: ec93bf58 00000000 ec91d080 ec91b200 c0032e61 00000000 00000000 00000000
   36.27> [    3.252055] bf60: 00000000 c0036c43 365bbdba 00000000 b69aa0fd ec91b200 00000000 00000000
   36.27> [    3.260269] bf80: ec93bf80 ec93bf80 00000001 00010001 ec93bf90 ec93bf90 ec93bfa0 ec91d080
   36.27> [    3.268482] bfa0: c0036bc1 00000000 00000000 c000cce5 00000000 00000000 00000000 00000000
   36.27> [    3.276694] bfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
   36.27> [    3.284907] bfe0: 00000000 00000000 00000000 00000000 00000013 00000000 1f216bd5 3ef08766
   36.28> [    3.293125] [<c0036f00>] (kthread_data) from [<c0033825>] (wq_worker_sleeping+0x9/0x80)
   36.28> [    3.301172] [<c0033825>] (wq_worker_sleeping) from [<c037467f>] (__schedule+0x1ff/0x338)
   36.28> [    3.309301] Code: 4770 bf00 f8d0 324c (f853) 0c14 
   36.28> [    3.314112] ---[ end trace 71ceb00d040f19ef ]---
   36.28> [    3.318746] Fixing recursive fault but reboot is needed!

0 samgyung zhang over 8 years ago in reply to Venkat Mandela

Expert 1060 points

Hi,venkat,
Can you find out any problem that i had mensioned in the last discussion ten days ago?
Hope to get some message from you soon,thanks very much!

0 Venkat Mandela over 8 years ago in reply to samgyung zhang

TI__Expert 5970 points

samgyung,

Is this error message you attached on the EVM or on your hardware? I will recheck the patches on a DRA72 EVM. You are not expected to see a kernel crash.

regards,
Venkat

0 samgyung zhang over 8 years ago in reply to Venkat Mandela

Expert 1060 points

HI，venkat,

Thank for your patience!My EVM board is based on DRA74X,not DRA72X.Dra74x has two DPLL_VIDEO,but DRA72X only has one DPLL_VIDEO.So i has not checked on the evm board.It was attached on my hardware.

Thanks very much!

0 Venkat Mandela over 8 years ago in reply to samgyung zhang

TI__Expert 5970 points

Samgyung,

If you are using DR74x which has two video PLL's , you should not have a problem at all. All the patches I shared were assuming that you were on DRA722 based on the subject of the post "Linux/DRA722: dra722/dra725"

If you look at dra7-evm.dts, we have entries for a 2nd LCD panel using VOUT3 connected over FPDLink. This has been tested concurrently with the LCD. You can see the below dts files and update your dts configuration. You should not need any kernel patches.

2nd LCD Panel entries

review.omapzoom.org/gitweb

review.omapzoom.org/gitweb

dra7xx-evm-lcd10.dtsi

review.omapzoom.org/gitweb

dra7-evm-lcd10.dts
review.omapzoom.org/gitweb

regards,
Venkat

0 samgyung zhang over 8 years ago in reply to Venkat Mandela

Expert 1060 points

Hi,venkat,

I think you have misunderstood me.My EVM board is based on DRA74x,but the products of my company is based on DRA722.

0 Venkat Mandela over 8 years ago in reply to samgyung zhang

TI__Expert 5970 points

Hi,

I have was able to reproduce the issue you described and was able to fix it with the below patch. Can you please apply this patch on top of the four patches provided earlier and test?

review.omapzoom.org/38548 HACK: read VOUT2 PLL information from Video1 PLL

regards,
Venkat

0 samgyung zhang over 8 years ago in reply to Venkat Mandela

Expert 1060 points

Hi,
Sorry for late respond!I was quiet bussy this period of time.I have verified the patch and it work,thank you very much!Hope you have a good day!

Processors

Processors forum

Linux/DRA722: dra722/dra725