We have a custom board based on the CC2640R2FYFVR 2.7x2.7 mm WCSP. I took the BLE5 Simple Peripheral application, copied it into a new project, modified the board files to match the pin definitions for our board, made the other associated changes to direct the build to use these files, and am running this firmware on our board. (Using CCS v10 for development)
The device advertises successfully, and the signal strength looks good, but we have been unsuccessful in actually establishing a connection with any client apps.
The previous post on this issue, though with a different CC2640R2F variant, mentions the possibility of issues with the RF front end configuration and/or with the 32 kHz external crystal. With regard to the front end configuration, the documentation in the [board name].h, and the code in [board name].c files raise some questions. From the [board file].h comments:
* Define only one symbol:
* CC2650EM_7ID - Differential RF and internal biasing
(default for CC2640R2 LaunchPad)
* CC2650EM_5XD – Differential RF and external biasing
* CC2650EM_4XS – Single-ended RF on RF-P and external biasing
* CC2640R2DK_CXS - WCSP: Single-ended RF on RF-N and external biasing
* (Note that the WCSP is only tested and characterized for
* single ended configuration, and it has a WCSP-specific
* PA table)
The comment for WCSP mentions single-ended RF configuration, but our board uses differential RF and internal biasing. Initial testing was with the CC2650EM_7ID setting since the comment indicates this is the one for differential RF and internal biasing, but the comment about WCSP raises the question as to whether this will work.
The CC2640R2DK_CXS setting does not actually appear in ble_user_config.c, but CC2640R2EM_CXS does. I tried building the firmware with this value, but the behavior was the same, which is to be expected since the board is not actually using single-ended RF.
The value used here also affects the transmit power table used, so it’s not clear on how to set up the RF configuration for a CC2640R2FYFVR using differential RF and internal biasing with the appropriate transmit power table. Should all settings associated with CC2650EM_71D work with our board? Should I set up a different #define to direct it to use the transmit power table for WCSP defined in ble_user_config.c, even though the comments indicate it is intended for single-ended output?
For the 32 kHz crystal, we have an external 32 kHz crystal connected at X32K_Q1 and X32K_Q2. Board space is extremely limited, and there are no external capacitors connected to the crystal. The data sheet for the crystal indicates a load capacitance of 7 pF, which is within the 6 to 12 pF range required for the CC2640R2F. The low-frequency oscillator is configured as follows in ccfg.c:
//#####################################
// Clock settings
//#####################################
#ifndef SET_CCFG_MODE_CONF_SCLK_LF_OPTION
// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x0 // LF clock derived from High Frequency XOSC
// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x1 // External LF clock
#define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x2 // LF XOSC
// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x3 // LF RCOSC
#endif
#ifndef SET_CCFG_MODE_CONF_XOSC_CAP_MOD
// #define SET_CCFG_MODE_CONF_XOSC_CAP_MOD 0x0 // Apply cap-array delta
#define SET_CCFG_MODE_CONF_XOSC_CAP_MOD 0x1 // Don't apply cap-array delta
#endif
#ifndef SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA
#define SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA 0xFF // Signed 8-bit value, directly modifying trimmed XOSC cap-array value
#endif
#ifndef SET_CCFG_EXT_LF_CLK_DIO
#define SET_CCFG_EXT_LF_CLK_DIO 0x01 // DIO number if using external LF clock
#endif
#ifndef SET_CCFG_EXT_LF_CLK_RTC_INCREMENT
#define SET_CCFG_EXT_LF_CLK_RTC_INCREMENT 0x800000 // RTC increment representing the external LF clock frequency
#endif
The CC13x0, CC26x0 SimpleLink Wireless MCU Technical Reference Manual, August 2017 revision, includes a diagram (Figure 6-5. System Clock Muxing) that shows DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL and DDI_0_OSC:CTL0.XOSC_LF_DIG_BYPASS signals used to select the external 32 kHz crystal as the low-frequency clock source. I am assuming that the line
#define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x2 // LF XOSC
Results in the proper setting of these signals as I do not see these manipulated in code (though I have not dug into the TI-RTOS code at this point).
As suggested in another post, I have turned off POWER_SAVING as a possible way to determine whether the 32 kHz crystal is contributing to the issue, but the behavior is the same with POWER_SAVING on or off.
As we continue to dig into this any suggestions/direction on where to look would be appreciated.
Thanks very much.
