Part Number: MSPM0G1518
Other Parts Discussed in Thread: LP-MSPM0G3519, MSPM0G1507
Hello,
in our current project were running the following configuration on a MSPM0G1518:
- CPU clock @ 78MHz, ULPCLK @ 39MHz
- TIMG7 triggers interrupt every 100 µs
- In an interrupt handler SYSTICK timer is started and every 10th call of interrupt handler SYSTICK counter value is read and SYSTICK timer is restarted (used for CPU Load calculation)
- Every call of interrupt handler ADC conversion is started (2 ADCs with sequence of 10 signals each), in every 10th call of interrupt handler the a DMA is configured to transmit the results
The somehow weird behaviors we see (described for MEMRES8 of ADC0, but they are present for all other MEMRES of ADC0 as well, but with varying amplitude for the peaks/ drops):
- The overall "stable" results vary over multiple MCU resets between 2 values: sometimes it's 490, sometimes 515 for the given input voltage
- Every 10th conversion (the one which is started along the DMA) the result varies from the other 9. When the "stable" result is 490, then we see a peak to 515, when stable is 515 we see a drop to 490.
The amplitude of the peak/ drop although reduces, when the CPU clock and ULPCLK is reduced to 32MHz).
Both behaviors we only see for ADC0, results of ADC1 are stable and don't show variation or drops.
When running both ADCs non synchronized at different timings (different conversion times, different clock divs or different source) both described effects completely disappear. Also when not starting conversion of ADC1, the ADC0 doesn't show the issue anymore.
We also checked the interrupt handler including the ADC conversions/DMAs never exceeding the 100µs. They finish 15-20 µs before the next interrupt triggers.
We tried figuring out the issue with a reduced project. Although the peaks/ drops appear much less frequent (over multiple resets), they are not gone completely. The variation of the "stable" result still persists as well.
As already mentioned, our interrupt routine in the project includes some more code, but cannot be published here.
The point that the peak/ drop error occurs less frequent, when the interrupt routine is smaller made us think, we have a timing issue. But as I said, timing was checked and is fine. There are no overlapping interrupt routines/ ADC conversions.
This issue was also reproduced using a LP-MSPM0G3519 as well as MSPM0G1507.
