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The BUFFER TYPE column of the Pin Attributes table in the Datasheet can be used to identify which pins on the device use the LVCMOS buffer
The *_PADCONFIGn registers in the Control Module (CTRL_MMR) are used to program the Drive Strength of LVCMOS buffers
See the REGISTER NAME column of the Pin Multiplexing table in the Datasheet to determine the *_PADCONFIGn associated with a LVCMOS pin/ball
The DRV_STR field (bits 20-19) of the *_PADCONFIGn register is the 2-bit field where the Drive Strength is programmed:
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Drive Strength Control Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types). Nominal drive strength is recommended and is the value used for data manual AC timing. Fast or Slow modes can be used where necessary, and should be validated using IBIS simulations to determine the appropriate timing derate from the data manual. 0h - Nominal (recommended) 1h - Fast 2h - Slow 3h- Reserved |
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Datasheet IO timings are based on the NOM setting in the *_PADCONFIGn register(s). The NOM setting is generally recommended.
Source synchronous interfaces can use FAST/SLOW with negligible effect on the IO timings.
For Interfaces with a mix of Inputs and Outputs, IBIS simulations can be performed by the user to quantify the impact to IO timings in their system if the FAST/SLOW settings are used. This is due to the shift in the 50% crossing point of the Output signals between NOM and FAST/SLOW configurations.
IBIS Models for the LVCMOS buffers are provided for both 1.8V (1p8) and 3.3V (3p3) operation, and for the three drive strength options (Nom, Slow, Fast). There are also separate models for the two physical layouts of the LVCMOS buffers (L, H). This IBIS model contains the mapping of each LVCMOS pin to either the LVCMOS_H or LVCMOS_L version of buffer.
Any LVCMOS models with the term "UT" in the model name are Reserved and should not be used.
An excerpt from an IBIS Model with LVCMOS Model Selectors is shown below as an example.
|********** LVCMOS
[Model Selector] LVCMOS_H
lvcmos1_nom_1p8_h PRWDWUWSWEWCDGLVCMOS_H@_Nom_1p8_comment
lvcmos1_nom_3p3_h PRWDWUWSWEWCDGLVCMOS_H@_Nom_3p3_comment
lvcmos1_slow_1p8_h PRWDWUWSWEWCDGLVCMOS_H@_Slow_1p8_comment
lvcmos1_slow_3p3_h PRWDWUWSWEWCDGLVCMOS_H@_Slow_3p3_comment
lvcmos1_fast_1p8_h PRWDWUWSWEWCDGLVCMOS_H@_Fast_1p8_comment
lvcmos1_fast_3p3_h PRWDWUWSWEWCDGLVCMOS_H@_Fast_3p3_comment
|
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[Model Selector] LVCMOS_V
lvcmos0_nom_1p8_v PRWDWUWSWEWCDGLVCMOS_V@_Nom_1p8_comment
lvcmos0_nom_3p3_v PRWDWUWSWEWCDGLVCMOS_V@_Nom_3p3_comment
lvcmos0_slow_1p8_v PRWDWUWSWEWCDGLVCMOS_V@_Slow_1p8_comment
lvcmos0_slow_3p3_v PRWDWUWSWEWCDGLVCMOS_V@_Slow_3p3_comment
lvcmos0_fast_1p8_v PRWDWUWSWEWCDGLVCMOS_V@_Fast_1p8_comment
lvcmos0_fast_3p3_v PRWDWUWSWEWCDGLVCMOS_V@_Fast_3p3_comment
The BUFFER TYPE column of the Pin Attributes table in the Datasheet can be used to identify which pins on the device use the SDIO buffer.
The *_SDIOn_CTRL registers in the Control Module (CTRL_MMR) are used to program the Drive Strength of SDIO buffers.
Specifically, the *_SDIO1_CTRL register controls the drive strength of the mmc1_* pins, *_SDIO2_CTRL controls the mmc2_* pins, etc.
The DRV_STR field (bits 4-0) of the *_SDIOn_CTRL registers is the 5-bit field where the SDIO Drive Strength is programmed:
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Drive Strength Control. Selects the drive strength value for SDIO pins. For options other than the Reset/Default 40ohm, the Reset/Default register value should be modified by the listed value below. Reset/Default 40ohms Reset/Default + 5d 33ohms Reset/Default - 5d 50ohms Reset/Default - 10d 66ohms |
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Datasheet IO timings are based on the Default 40ohm setting in the *_SDIOn_CTRL registers. The 40ohm setting is generally recommended.
IBIS simulations can be performed by the user to quantify the impact to IO timings in their system if the other drive strength settings are used. This is due to the shift in the 50% crossing point of the Output signals between the 40ohm and non-40ohm configurations.
IBIS Models for the SDIO buffers are provided for both 1.8V (1p8) and 3.3V (3p3) operation, and for the four drive strength options (R33=33ohm, R40=40ohm, R50=50ohm, R66=66ohm).
Any SDIO models with the term "UT" in the model name are Reserved and should not be used.
An excerpt from an IBIS Model with an SDIO Model Selector is shown below as an example.
|****************** SDIO
[Model Selector] SDIO_H
sdio1_r33_1p8_h PRWDWUWSWEWCDGSDIO_H@_R33_1p8_comment
sdio1_r33_3p3_h PRWDWUWSWEWCDGSDIO_H@_R33_3p3_comment
sdio1_r40_1p8_h PRWDWUWSWEWCDGSDIO_H@_R40_1p8_comment
sdio1_r40_3p3_h PRWDWUWSWEWCDGSDIO_H@_R40_3p3_comment
sdio1_r50_1p8_h PRWDWUWSWEWCDGSDIO_H@_R50_1p8_comment
sdio1_r50_3p3_h PRWDWUWSWEWCDGSDIO_H@_R50_3p3_comment
sdio1_r66_1p8_h PRWDWUWSWEWCDGSDIO_H@_R66_1p8_comment
sdio1_r66_3p3_h PRWDWUWSWEWCDGSDIO_H@_R66_3p3_comment
The BUFFER TYPE column of the Pin Attributes table in the Datasheet can be used to identify which pins on the device use the eMMCPHY buffer.
The PHY_CTRL_1_REG registers in the MMCSD module are used to program the Drive Strength of eMMCPHY buffers.
Specifically, the MMCSD0 PHY_CTRL_1_REG register controls the drive strength of the mmc0_* pins.
The DR_TY field (bits 22-20) of the PHY_CTRL_1_REG registers is the 3-bit field where the eMMCPHY Drive Strength is programmed:
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Drive Source/Sink Impedance Programming 0h: 50 Ohms 1h: 33 Ohms 2h: 66 Ohms 3h: 100 Ohms 4h: 40 Ohms |
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Datasheet IO timings are based on the Default 50ohm setting in the PHY_CTRL_1_REG registers. The 50ohm setting is generally recommended.
IBIS simulations can be performed by the user to quantify the impact to IO timings in their system if the other drive strength settings are used. This is due to the shift in the 50% crossing point of the Output signals between the 50ohm and non-50ohm configurations.
IBIS Models for the SDIO buffers are provided for the five drive strength options (33ohm, 40ohm, 50ohm, 66ohm, 100ohm).
An excerpt from an IBIS Model with an EMMC Model Selector is shown below as an example.
|*****************************************************************************************
| EMMC
|*****************************************************************************************
[MODEL SELECTOR] EMMC
emmc51_io_tx33ohm 33ohm DRIVER
emmc51_io_tx40ohm 40ohm DRIVER
emmc51_io_tx50ohm 50ohm DRIVER
emmc51_io_tx66ohm 66ohm DRIVER
emmc51_io_tx100ohm 100ohm DRIVER
See Section 2.3 of the Jacinto 7 DDRSS Register Configuration Tool (https://www.ti.com/lit/pdf/spracu8) for details on the Drive Strength controls for the DDR IO.
