[FAQ] TDA4VM: How do I port an R5F RTOS Ethernet client running on MCU2_1 to other R5F cores (ex: MCU3_0 core) in SoCs with multiple R5F cores?

From 03a33c9a2d8dbbcb6f1564d671426e20a7ead6c7 Mon Sep 17 00:00:00 2001
From: sudheer <s-doredla@ti.com>
Date: Wed, 29 Mar 2023 19:40:51 +0530
Subject: [PATCH] ethfw: client: MCU_3_0 support

Reference code to enable RTOS client support on mcu3_0 core in J721E
device as a replacement for mcu2_1 core which is supported by default.
It does NOT aim at adding suppor tmcu3_0 in addition to mcu2_1.

The changes are summarized below:

 - Replace IPC id of the RTOS client (IPC_MCU2_1 -> IPC_MCU3_0) in
   EthFw library, CpswProxy server and client, as well as EthFw server
   app.
 - Replace IPC core id where virtual switch port and virtual MAC port
   interfaces are enabled on.
 - Update memory addresses used for MCU3_0 IPC (0xA3000000 -> 0xA4000000).
 - Rename intercore macros as per corresponding changes in Enet LLD
   for mcu3_0 support.
 - Enabling mcu3_0 core in driver's CORELIST
    * Core Enet LLD driver support only
    * No examples are being enabled
 - Replace mcu2_1 with mcu3_0 in intercore and lwipific libraries
    * Meant for cases where RTOS client core is mcu3_0, not mcu2_1
    * No intention to support mcu3_0 in addition to mcu2_1

Signed-off-by: sudheer <s-doredla@ti.com>
---
 .../{mcu_2_1 => mcu_3_0}/concerto.mak         |  4 +-
 .../j7200/linker_mem_map.cmd                  | 12 ++--
 .../j721e/linker_mem_map.cmd                  | 12 ++--
 .../j784s4/linker_mem_map.cmd                 | 12 ++--
 .../{mcu_2_1 => mcu_3_0}/linker_freertos.cmd  | 56 +++++++++----------
 .../{mcu_2_1 => mcu_3_0}/linker_safertos.cmd  | 30 +++++-----
 .../linker_safertos_j7200.cmd                 | 30 +++++-----
 .../{mcu_2_1 => mcu_3_0}/main.c               | 10 ++--
 .../app_remoteswitchcfg_server/mcu_2_0/main.c | 32 +++++------
 ethfw/apps/common/r5f_mpu_j721e_default.c     |  4 +-
 ethfw/apps/common/r5f_mpu_j721e_safertos.c    |  4 +-
 ethfw/apps/common/r5f_mpu_j784s4_default.c    |  4 +-
 ethfw/apps/common/r5f_mpu_j784s4_safertos.c   |  4 +-
 ethfw/ethfw/src/ethfw.c                       |  2 +-
 ethfw/ethfw_build_flags.mak                   |  4 +-
 ethfw/ethremotecfg/client/src/cpsw_proxy.c    |  2 +-
 .../packages/ti/drv/enet/enet_component.mk    |  4 +-
 .../ti/drv/enet/intercore/include/ic_ipc.h    |  2 +-
 .../ti/drv/enet/intercore/include/ic_queue.h  |  8 +--
 .../ti/drv/enet/lwipific/inc/bufpool.h        |  6 +-
 .../ti/drv/enet/lwipific/inc/lwip2enet_ic.h   | 12 ++--
 .../ti/drv/enet/lwipific/src/lwip2enet_ic.c   | 26 ++++-----
 .../ti/drv/enet/soc/j7x/j721e/enet_soc.c      | 22 +++++++-
 23 files changed, 161 insertions(+), 141 deletions(-)
 rename ethfw/apps/app_remoteswitchcfg_client/{mcu_2_1 => mcu_3_0}/concerto.mak (97%)
 rename ethfw/apps/app_remoteswitchcfg_client/{mcu_2_1 => mcu_3_0}/j7200/linker_mem_map.cmd (92%)
 rename ethfw/apps/app_remoteswitchcfg_client/{mcu_2_1 => mcu_3_0}/j721e/linker_mem_map.cmd (92%)
 rename ethfw/apps/app_remoteswitchcfg_client/{mcu_2_1 => mcu_3_0}/j784s4/linker_mem_map.cmd (92%)
 rename ethfw/apps/app_remoteswitchcfg_client/{mcu_2_1 => mcu_3_0}/linker_freertos.cmd (75%)
 rename ethfw/apps/app_remoteswitchcfg_client/{mcu_2_1 => mcu_3_0}/linker_safertos.cmd (91%)
 rename ethfw/apps/app_remoteswitchcfg_client/{mcu_2_1 => mcu_3_0}/linker_safertos_j7200.cmd (91%)
 rename ethfw/apps/app_remoteswitchcfg_client/{mcu_2_1 => mcu_3_0}/main.c (99%)

diff --git a/ethfw/apps/app_remoteswitchcfg_client/mcu_2_1/concerto.mak b/ethfw/apps/app_remoteswitchcfg_client/mcu_3_0/concerto.mak
similarity index 97%
rename from ethfw/apps/app_remoteswitchcfg_client/mcu_2_1/concerto.mak
rename to ethfw/apps/app_remoteswitchcfg_client/mcu_3_0/concerto.mak
index 3a23e13e..58d9cb56 100755
--- a/ethfw/apps/app_remoteswitchcfg_client/mcu_2_1/concerto.mak
+++ b/ethfw/apps/app_remoteswitchcfg_client/mcu_3_0/concerto.mak
@@ -2,10 +2,10 @@
 
 include $(PRELUDE)
 
-ifeq ($(BUILD_CPU_MCU2_1),yes)
+ifeq ($(BUILD_CPU_MCU3_0),yes)
 ifneq (,$(filter $(TARGET_CPU),R5F R5Ft))
 
-CPU_ID=mcu2_1
+CPU_ID=mcu3_0
 
 TARGET      := app_remoteswitchcfg_client
 TARGETTYPE  := exe
diff --git a/ethfw/apps/app_remoteswitchcfg_client/mcu_2_1/j7200/linker_mem_map.cmd b/ethfw/apps/app_remoteswitchcfg_client/mcu_3_0/j7200/linker_mem_map.cmd
similarity index 92%
rename from ethfw/apps/app_remoteswitchcfg_client/mcu_2_1/j7200/linker_mem_map.cmd
rename to ethfw/apps/app_remoteswitchcfg_client/mcu_3_0/j7200/linker_mem_map.cmd
index b2d88ddf..39e57c24 100644
--- a/ethfw/apps/app_remoteswitchcfg_client/mcu_2_1/j7200/linker_mem_map.cmd
+++ b/ethfw/apps/app_remoteswitchcfg_client/mcu_3_0/j7200/linker_mem_map.cmd
@@ -71,12 +71,12 @@ MEMORY
     R5F_TCMA                 (    X ) : ORIGIN = 0x00000100 , LENGTH = 0x00007F00
     /* R5F_TCMB0 [ size 32.00 KB ] */
     R5F_TCMB0                ( RWIX ) : ORIGIN = 0x41010000 , LENGTH = 0x00008000
-    /* DDR for MCU2_1 for Linux IPC [ size 1024.00 KB ] */
-    DDR_MCU2_1_IPC           ( RWIX ) : ORIGIN = 0xA3000000 , LENGTH = 0x00100000
-    /* DDR for MCU2_1 for Linux resource table [ size 1024 B ] */
-    DDR_MCU2_1_RESOURCE_TABLE ( RWIX ) : ORIGIN = 0xA3100000 , LENGTH = 0x00000400
-    /* DDR for MCU2_1 for code/data [ size 63.00 MB ] */
-    DDR_MCU2_1               ( RWIX ) : ORIGIN = 0xA3100400 , LENGTH = 0x00EFFC00
+    /* DDR for MCU3_0 for Linux IPC [ size 1024.00 KB ] */
+    DDR_MCU3_0_IPC           ( RWIX ) : ORIGIN = 0xA3000000 , LENGTH = 0x00100000
+    /* DDR for MCU3_0 for Linux resource table [ size 1024 B ] */
+    DDR_MCU3_0_RESOURCE_TABLE ( RWIX ) : ORIGIN = 0xA3100000 , LENGTH = 0x00000400
+    /* DDR for MCU3_0 for code/data [ size 63.00 MB ] */
+    DDR_MCU3_0               ( RWIX ) : ORIGIN = 0xA3100400 , LENGTH = 0x00EFFC00
     /* Memory for remote core logging [ size 256.00 KB ] */
     APP_LOG_MEM                       : ORIGIN = 0xB8000000 , LENGTH = 0x00040000
     /* Memory for TI OpenVX shared memory. MUST be non-cached or cache-coherent [ size 31.75 MB ] */
diff --git a/ethfw/apps/app_remoteswitchcfg_client/mcu_2_1/j721e/linker_mem_map.cmd b/ethfw/apps/app_remoteswitchcfg_client/mcu_3_0/j721e/linker_mem_map.cmd
similarity index 92%
rename from ethfw/apps/app_remoteswitchcfg_client/mcu_2_1/j721e/linker_mem_map.cmd
rename to ethfw/apps/app_remoteswitchcfg_client/mcu_3_0/j721e/linker_mem_map.cmd
index b84ae5af..3e6fbf05 100644
--- a/ethfw/apps/app_remoteswitchcfg_client/mcu_2_1/j721e/linker_mem_map.cmd
+++ b/ethfw/apps/app_remoteswitchcfg_client/mcu_3_0/j721e/linker_mem_map.cmd
@@ -71,12 +71,12 @@ MEMORY
     R5F_TCMA                 (    X ) : ORIGIN = 0x00000100 , LENGTH = 0x00007F00
     /* R5F_TCMB0 [ size 32.00 KB ] */
     R5F_TCMB0                ( RWIX ) : ORIGIN = 0x41010000 , LENGTH = 0x00008000
-    /* DDR for MCU2_1 for Linux IPC [ size 1024.00 KB ] */
-    DDR_MCU2_1_IPC           ( RWIX ) : ORIGIN = 0xA3000000 , LENGTH = 0x00100000
-    /* DDR for MCU2_1 for Linux resource table [ size 1024 B ] */
-    DDR_MCU2_1_RESOURCE_TABLE ( RWIX ) : ORIGIN = 0xA3100000 , LENGTH = 0x00000400
-    /* DDR for MCU2_1 for code/data [ size 63.00 MB ] */
-    DDR_MCU2_1               ( RWIX ) : ORIGIN = 0xA3100400 , LENGTH = 0x00EFFC00
+    /* DDR for MCU3_0 for Linux IPC [ size 1024.00 KB ] */
+    DDR_MCU3_0_IPC           ( RWIX ) : ORIGIN = 0xA4000000 , LENGTH = 0x00100000
+    /* DDR for MCU3_0 for Linux resource table [ size 1024 B ] */
+    DDR_MCU3_0_RESOURCE_TABLE ( RWIX ) : ORIGIN = 0xA4100000 , LENGTH = 0x00000400
+    /* DDR for MCU3_0 for code/data [ size 63.00 MB ] */
+    DDR_MCU3_0               ( RWIX ) : ORIGIN = 0xA4100400 , LENGTH = 0x00EFFC00
     /* Memory for remote core logging [ size 256.00 KB ] */
     APP_LOG_MEM                       : ORIGIN = 0xB8000000 , LENGTH = 0x00040000
     /* Memory for TI OpenVX shared memory. MUST be non-cached or cache-coherent [ size 31.75 MB ] */
diff --git a/ethfw/apps/app_remoteswitchcfg_client/mcu_2_1/j784s4/linker_mem_map.cmd b/ethfw/apps/app_remoteswitchcfg_client/mcu_3_0/j784s4/linker_mem_map.cmd
similarity index 92%
rename from ethfw/apps/app_remoteswitchcfg_client/mcu_2_1/j784s4/linker_mem_map.cmd
rename to ethfw/apps/app_remoteswitchcfg_client/mcu_3_0/j784s4/linker_mem_map.cmd
index c30d0c1c..a1c03b4d 100644
--- a/ethfw/apps/app_remoteswitchcfg_client/mcu_2_1/j784s4/linker_mem_map.cmd
+++ b/ethfw/apps/app_remoteswitchcfg_client/mcu_3_0/j784s4/linker_mem_map.cmd
@@ -71,12 +71,12 @@ MEMORY
     R5F_TCMA                 (    X ) : ORIGIN = 0x00000100 , LENGTH = 0x00007F00
     /* R5F_TCMB0 [ size 32.00 KB ] */
     R5F_TCMB0                ( RWIX ) : ORIGIN = 0x41010000 , LENGTH = 0x00008000
-    /* DDR for MCU2_1 for Linux IPC [ size 1024.00 KB ] */
-    DDR_MCU2_1_IPC           ( RWIX ) : ORIGIN = 0xA3000000 , LENGTH = 0x00100000
-    /* DDR for MCU2_1 for Linux resource table [ size 1024 B ] */
-    DDR_MCU2_1_RESOURCE_TABLE ( RWIX ) : ORIGIN = 0xA3100000 , LENGTH = 0x00000400
-    /* DDR for MCU2_1 for code/data [ size 63.00 MB ] */
-    DDR_MCU2_1               ( RWIX ) : ORIGIN = 0xA3100400 , LENGTH = 0x00EFFC00
+    /* DDR for MCU3_0 for Linux IPC [ size 1024.00 KB ] */
+    DDR_MCU3_0_IPC           ( RWIX ) : ORIGIN = 0xA4000000 , LENGTH = 0x00100000
+    /* DDR for MCU3_0 for Linux resource table [ size 1024 B ] */
+    DDR_MCU3_0_RESOURCE_TABLE ( RWIX ) : ORIGIN = 0xA4100000 , LENGTH = 0x00000400
+    /* DDR for MCU3_0 for code/data [ size 63.00 MB ] */
+    DDR_MCU3_0               ( RWIX ) : ORIGIN = 0xA4100400 , LENGTH = 0x00EFFC00
     /* Memory for remote core logging [ size 256.00 KB ] */
     APP_LOG_MEM                       : ORIGIN = 0xB8000000 , LENGTH = 0x00040000
     /* Memory for TI OpenVX shared memory. MUST be non-cached or cache-coherent [ size 31.75 MB ] */
diff --git a/ethfw/apps/app_remoteswitchcfg_client/mcu_2_1/linker_freertos.cmd b/ethfw/apps/app_remoteswitchcfg_client/mcu_3_0/linker_freertos.cmd
similarity index 75%
rename from ethfw/apps/app_remoteswitchcfg_client/mcu_2_1/linker_freertos.cmd
rename to ethfw/apps/app_remoteswitchcfg_client/mcu_3_0/linker_freertos.cmd
index 9df357a3..6e8716eb 100644
--- a/ethfw/apps/app_remoteswitchcfg_client/mcu_2_1/linker_freertos.cmd
+++ b/ethfw/apps/app_remoteswitchcfg_client/mcu_3_0/linker_freertos.cmd
@@ -64,66 +64,66 @@ SECTIONS
         *(.text:Udma_ringDequeueRaw*)
         *(.text:Udma_virtToPhyFxn*)
 */
-     }     > DDR_MCU2_1
+     }     > DDR_MCU3_0
 
     .text_rest{
        _text_rest_begin = .;
        *(.text)
        _text_rest_end = .;
-    } palign(32)    >  DDR_MCU2_1
+    } palign(32)    >  DDR_MCU3_0
 
-    .const              : {} palign(8)      > DDR_MCU2_1
-    .rodata             : {} palign(8)      > DDR_MCU2_1
-    .cinit              : {} palign(8)      > DDR_MCU2_1
+    .const              : {} palign(8)      > DDR_MCU3_0
+    .rodata             : {} palign(8)      > DDR_MCU3_0
+    .cinit              : {} palign(8)      > DDR_MCU3_0
     .pinit              : {} palign(8)      > R5F_TCMB0
-    .bss                : {} align(4)       > DDR_MCU2_1
-    .far                : {} align(4)       > DDR_MCU2_1
-    .data               : {} palign(128)    > DDR_MCU2_1
-    .sysmem             : {}                > DDR_MCU2_1
-    .data_buffer        : {} palign(128)    > DDR_MCU2_1
-    .bss.devgroup*      : {} align(4)       > DDR_MCU2_1
-    .const.devgroup*    : {} align(4)       > DDR_MCU2_1
-    .boardcfg_data      : {} align(4)       > DDR_MCU2_1
-
-    ipc_data_buffer (NOINIT) : {} palign(128)   > DDR_MCU2_1
+    .bss                : {} align(4)       > DDR_MCU3_0
+    .far                : {} align(4)       > DDR_MCU3_0
+    .data               : {} palign(128)    > DDR_MCU3_0
+    .sysmem             : {}                > DDR_MCU3_0
+    .data_buffer        : {} palign(128)    > DDR_MCU3_0
+    .bss.devgroup*      : {} align(4)       > DDR_MCU3_0
+    .const.devgroup*    : {} align(4)       > DDR_MCU3_0
+    .boardcfg_data      : {} align(4)       > DDR_MCU3_0
+
+    ipc_data_buffer (NOINIT) : {} palign(128)   > DDR_MCU3_0
     .resource_table          :
     {
         __RESOURCE_TABLE = .;
-    }                                           > DDR_MCU2_1_RESOURCE_TABLE
+    }                                           > DDR_MCU3_0_RESOURCE_TABLE
 
     intercore_eth_desc_mem (NOLOAD) : {} palign(128) > INTERCORE_ETH_DESC_MEM
     intercore_eth_data_mem (NOLOAD) : {} palign(128) > INTERCORE_ETH_DATA_MEM
 
-    .tracebuf                : {} align(1024)   > DDR_MCU2_1
+    .tracebuf                : {} align(1024)   > DDR_MCU3_0
 
-    .bss:ENET_DMA_DESC_MEMPOOL  (NOLOAD) {} ALIGN (128) > DDR_MCU2_1
-    .bss:ENET_DMA_RING_MEMPOOL  (NOLOAD) {} ALIGN (128) > DDR_MCU2_1
-    .bss:ENET_DMA_PKT_MEMPOOL   (NOLOAD) {} ALIGN (128) > DDR_MCU2_1
-    .bss:ENET_DMA_OBJ_MEM       (NOLOAD) {} ALIGN (128) > DDR_MCU2_1
+    .bss:ENET_DMA_DESC_MEMPOOL  (NOLOAD) {} ALIGN (128) > DDR_MCU3_0
+    .bss:ENET_DMA_RING_MEMPOOL  (NOLOAD) {} ALIGN (128) > DDR_MCU3_0
+    .bss:ENET_DMA_PKT_MEMPOOL   (NOLOAD) {} ALIGN (128) > DDR_MCU3_0
+    .bss:ENET_DMA_OBJ_MEM       (NOLOAD) {} ALIGN (128) > DDR_MCU3_0
 
     .bss:app_log_mem        (NOLOAD) : {} > APP_LOG_MEM
     .bss:ipc_vring_mem      (NOLOAD) : {} > IPC_VRING_MEM
-    .bss:ddr_shared_mem     (NOLOAD) : {} > DDR_MCU2_1
+    .bss:ddr_shared_mem     (NOLOAD) : {} > DDR_MCU3_0
 
-    .stack                   : {} align(4)      > DDR_MCU2_1  (HIGH)
+    .stack                   : {} align(4)      > DDR_MCU3_0  (HIGH)
 
-    .irqStack   : {. = . + __IRQ_STACK_SIZE;} align(4)      > DDR_MCU2_1  (HIGH)
+    .irqStack   : {. = . + __IRQ_STACK_SIZE;} align(4)      > DDR_MCU3_0  (HIGH)
     RUN_START(__IRQ_STACK_START)
     RUN_END(__IRQ_STACK_END)
 
-    .fiqStack   : {. = . + __FIQ_STACK_SIZE;} align(4)      > DDR_MCU2_1  (HIGH)
+    .fiqStack   : {. = . + __FIQ_STACK_SIZE;} align(4)      > DDR_MCU3_0  (HIGH)
     RUN_START(__FIQ_STACK_START)
     RUN_END(__FIQ_STACK_END)
 
-    .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4)    > DDR_MCU2_1  (HIGH)
+    .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4)    > DDR_MCU3_0  (HIGH)
     RUN_START(__ABORT_STACK_START)
     RUN_END(__ABORT_STACK_END)
 
-    .undStack   : {. = . + __UND_STACK_SIZE;} align(4)      > DDR_MCU2_1  (HIGH)
+    .undStack   : {. = . + __UND_STACK_SIZE;} align(4)      > DDR_MCU3_0  (HIGH)
     RUN_START(__UND_STACK_START)
     RUN_END(__UND_STACK_END)
 
-    .svcStack   : {. = . + __SVC_STACK_SIZE;} align(4)      > DDR_MCU2_1  (HIGH)
+    .svcStack   : {. = . + __SVC_STACK_SIZE;} align(4)      > DDR_MCU3_0  (HIGH)
     RUN_START(__SVC_STACK_START)
     RUN_END(__SVC_STACK_END)
 }  /* end of SECTIONS */
diff --git a/ethfw/apps/app_remoteswitchcfg_client/mcu_2_1/linker_safertos.cmd b/ethfw/apps/app_remoteswitchcfg_client/mcu_3_0/linker_safertos.cmd
similarity index 91%
rename from ethfw/apps/app_remoteswitchcfg_client/mcu_2_1/linker_safertos.cmd
rename to ethfw/apps/app_remoteswitchcfg_client/mcu_3_0/linker_safertos.cmd
index 45dd05cf..84e52a52 100644
--- a/ethfw/apps/app_remoteswitchcfg_client/mcu_2_1/linker_safertos.cmd
+++ b/ethfw/apps/app_remoteswitchcfg_client/mcu_3_0/linker_safertos.cmd
@@ -71,46 +71,46 @@ SECTIONS
     {
         .KERNEL_FUNCTION LOAD_START( lnkKernelFuncStartAddr ),
                          LOAD_END( lnkKernelFuncEndAddr )       : {} palign( 0x10000 )
-    } > DDR_MCU2_1
+    } > DDR_MCU3_0
 
-    .text   : palign(32) >  DDR_MCU2_1
-    .rodata : palign(8) > DDR_MCU2_1
+    .text   : palign(32) >  DDR_MCU3_0
+    .rodata : palign(8) > DDR_MCU3_0
 
 
 
     .text_fast {
 
-    }     > DDR_MCU2_1
+    }     > DDR_MCU3_0
 
     .text_rest{
        _text_rest_begin = .;
        *(.text)
        _text_rest_end = .;
-    } palign(32)    >  DDR_MCU2_1
+    } palign(32)    >  DDR_MCU3_0
 
-    ipc_data_buffer (NOINIT) : {} palign(128)   > DDR_MCU2_1
+    ipc_data_buffer (NOINIT) : {} palign(128)   > DDR_MCU3_0
 
     .resource_table          :
     {
         __RESOURCE_TABLE = .;
-    }                                           > DDR_MCU2_1_RESOURCE_TABLE
+    }                                           > DDR_MCU3_0_RESOURCE_TABLE
 
     intercore_eth_desc_mem (NOLOAD) : {} palign(128) > INTERCORE_ETH_DESC_MEM
     intercore_eth_data_mem (NOLOAD) : {} palign(128) > INTERCORE_ETH_DATA_MEM
 
-    .tracebuf                : {} align(1024)   > DDR_MCU2_1
+    .tracebuf                : {} align(1024)   > DDR_MCU3_0
 
-    .bss:ENET_DMA_DESC_MEMPOOL  (NOLOAD) {} ALIGN (128) > DDR_MCU2_1
-    .bss:ENET_DMA_RING_MEMPOOL  (NOLOAD) {} ALIGN (128) > DDR_MCU2_1
-    .bss:ENET_DMA_PKT_MEMPOOL   (NOLOAD) {} ALIGN (128) > DDR_MCU2_1
-    .bss:ENET_DMA_OBJ_MEM       (NOLOAD) {} ALIGN (128) > DDR_MCU2_1
+    .bss:ENET_DMA_DESC_MEMPOOL  (NOLOAD) {} ALIGN (128) > DDR_MCU3_0
+    .bss:ENET_DMA_RING_MEMPOOL  (NOLOAD) {} ALIGN (128) > DDR_MCU3_0
+    .bss:ENET_DMA_PKT_MEMPOOL   (NOLOAD) {} ALIGN (128) > DDR_MCU3_0
+    .bss:ENET_DMA_OBJ_MEM       (NOLOAD) {} ALIGN (128) > DDR_MCU3_0
 
     /* Used in Switch configuration tool */
-    .serialContext     (NOLOAD) {} ALIGN (128) > DDR_MCU2_1
+    .serialContext     (NOLOAD) {} ALIGN (128) > DDR_MCU3_0
 
     .bss:app_log_mem        (NOLOAD) : {} > APP_LOG_MEM
     .bss:ipc_vring_mem      (NOLOAD) : {} > IPC_VRING_MEM
-    .bss:ddr_shared_mem     (NOLOAD) : {} > DDR_MCU2_1
+    .bss:ddr_shared_mem     (NOLOAD) : {} > DDR_MCU3_0
 
 /* Data sections. */
     GROUP  palign( 0x10000 ), LOAD_START( lnkRamStartAddr ), LOAD_END( lnkRamEndAddr )
@@ -149,7 +149,7 @@ SECTIONS
         .svcStack    END( lnkStacksEndAddr )    : {. = . + __SVC_STACK_SIZE;}   align(4)
         RUN_START(__SVC_STACK_START)
         RUN_END(__SVC_STACK_END)
-    } > DDR_MCU2_1
+    } > DDR_MCU3_0
 }
 
 /*-------------------------------- END ---------------------------------------*/
diff --git a/ethfw/apps/app_remoteswitchcfg_client/mcu_2_1/linker_safertos_j7200.cmd b/ethfw/apps/app_remoteswitchcfg_client/mcu_3_0/linker_safertos_j7200.cmd
similarity index 91%
rename from ethfw/apps/app_remoteswitchcfg_client/mcu_2_1/linker_safertos_j7200.cmd
rename to ethfw/apps/app_remoteswitchcfg_client/mcu_3_0/linker_safertos_j7200.cmd
index 01948fe7..ada597ed 100644
--- a/ethfw/apps/app_remoteswitchcfg_client/mcu_2_1/linker_safertos_j7200.cmd
+++ b/ethfw/apps/app_remoteswitchcfg_client/mcu_3_0/linker_safertos_j7200.cmd
@@ -71,46 +71,46 @@ SECTIONS
     {
         .KERNEL_FUNCTION LOAD_START( lnkKernelFuncStartAddr ),
                          LOAD_END( lnkKernelFuncEndAddr )       : {} palign( 0x10000 )
-    } > DDR_MCU2_1
+    } > DDR_MCU3_0
 
-    .text   : palign(32) >  DDR_MCU2_1
-    .rodata : palign(8) > DDR_MCU2_1
+    .text   : palign(32) >  DDR_MCU3_0
+    .rodata : palign(8) > DDR_MCU3_0
 
 
 
     .text_fast {
 
-    }     > DDR_MCU2_1
+    }     > DDR_MCU3_0
 
     .text_rest{
        _text_rest_begin = .;
        *(.text)
        _text_rest_end = .;
-    } palign(32)    >  DDR_MCU2_1
+    } palign(32)    >  DDR_MCU3_0
 
-    ipc_data_buffer (NOINIT) : {} palign(128)   > DDR_MCU2_1
+    ipc_data_buffer (NOINIT) : {} palign(128)   > DDR_MCU3_0
 
     .resource_table          :
     {
         __RESOURCE_TABLE = .;
-    }                                           > DDR_MCU2_1_RESOURCE_TABLE
+    }                                           > DDR_MCU3_0_RESOURCE_TABLE
 
     intercore_eth_desc_mem (NOLOAD) : {} palign(128) > INTERCORE_ETH_DESC_MEM
     intercore_eth_data_mem (NOLOAD) : {} palign(128) > INTERCORE_ETH_DATA_MEM
 
-    .tracebuf                : {} align(1024)   > DDR_MCU2_1
+    .tracebuf                : {} align(1024)   > DDR_MCU3_0
 
-    .bss:ENET_DMA_DESC_MEMPOOL  (NOLOAD) {} ALIGN (128) > DDR_MCU2_1
-    .bss:ENET_DMA_RING_MEMPOOL  (NOLOAD) {} ALIGN (128) > DDR_MCU2_1
-    .bss:ENET_DMA_PKT_MEMPOOL   (NOLOAD) {} ALIGN (128) > DDR_MCU2_1
-    .bss:ENET_DMA_OBJ_MEM       (NOLOAD) {} ALIGN (128) > DDR_MCU2_1
+    .bss:ENET_DMA_DESC_MEMPOOL  (NOLOAD) {} ALIGN (128) > DDR_MCU3_0
+    .bss:ENET_DMA_RING_MEMPOOL  (NOLOAD) {} ALIGN (128) > DDR_MCU3_0
+    .bss:ENET_DMA_PKT_MEMPOOL   (NOLOAD) {} ALIGN (128) > DDR_MCU3_0
+    .bss:ENET_DMA_OBJ_MEM       (NOLOAD) {} ALIGN (128) > DDR_MCU3_0
 
     /* Used in Switch configuration tool */
-    .serialContext     (NOLOAD) {} ALIGN (128) > DDR_MCU2_1
+    .serialContext     (NOLOAD) {} ALIGN (128) > DDR_MCU3_0
 
     .bss:app_log_mem        (NOLOAD) : {} > APP_LOG_MEM
     .bss:ipc_vring_mem      (NOLOAD) : {} > IPC_VRING_MEM
-    .bss:ddr_shared_mem     (NOLOAD) : {} > DDR_MCU2_1
+    .bss:ddr_shared_mem     (NOLOAD) : {} > DDR_MCU3_0
 
 /* Data sections. */
     GROUP  palign( 0x10000 ), LOAD_START( lnkRamStartAddr ), LOAD_END( lnkRamEndAddr )
@@ -149,7 +149,7 @@ SECTIONS
         .svcStack    END( lnkStacksEndAddr )    : {. = . + __SVC_STACK_SIZE;}   align(4)
         RUN_START(__SVC_STACK_START)
         RUN_END(__SVC_STACK_END)
-    } > DDR_MCU2_1
+    } > DDR_MCU3_0
 }
 
 /*-------------------------------- END ---------------------------------------*/
diff --git a/ethfw/apps/app_remoteswitchcfg_client/mcu_2_1/main.c b/ethfw/apps/app_remoteswitchcfg_client/mcu_3_0/main.c
similarity index 99%
rename from ethfw/apps/app_remoteswitchcfg_client/mcu_2_1/main.c
rename to ethfw/apps/app_remoteswitchcfg_client/mcu_3_0/main.c
index 9598ffc4..3f47bc16 100644
--- a/ethfw/apps/app_remoteswitchcfg_client/mcu_2_1/main.c
+++ b/ethfw/apps/app_remoteswitchcfg_client/mcu_3_0/main.c
@@ -241,7 +241,7 @@ static uint8_t gCntrlBuf[CPSW_REMOTE_APP_IPC_DATA_SIZE] __attribute__ ((section(
 
 static uint8_t g_vringMemBuf[IPC_VRING_MEM_SIZE] __attribute__ ((section(".bss:ipc_vring_mem"), aligned(8192)));
 
-static uint32_t selfProcId = IPC_MCU2_1;
+static uint32_t selfProcId = IPC_MCU3_0;
 static uint32_t gRemoteProc[] =
 {
 #if defined(SOC_J721E)
@@ -262,8 +262,8 @@ static uint32_t gNumRemoteProc = sizeof(gRemoteProc) / sizeof(uint32_t);
 static struct netif netif_ic;
 static uint32_t netif_ic_state[IC_ETH_MAX_VIRTUAL_IF] =
 {
-    IC_ETH_IF_MCU2_0_MCU2_1,
-    IC_ETH_IF_MCU2_1_MCU2_0,
+    IC_ETH_IF_MCU2_0_MCU3_0,
+    IC_ETH_IF_MCU3_0_MCU2_0,
     IC_ETH_IF_MCU2_0_A72
 };
 
@@ -1056,9 +1056,9 @@ static void EthApp_initNetif(CpswRemoteApp_VirtNetif *virtNetif)
         NETIF_SET_CHECKSUM_CTRL(netif, chksumFlags);
 #endif
 
-        /* Create inter-core virtual ethernet interface: MCU2_1 <-> MCU2_0 */
+        /* Create inter-core virtual ethernet interface: MCU3_0 <-> MCU2_0 */
         netif_add(&netif_ic, NULL, NULL, NULL,
-                  (void*)&netif_ic_state[IC_ETH_IF_MCU2_1_MCU2_0],
+                  (void*)&netif_ic_state[IC_ETH_IF_MCU3_0_MCU2_0],
                   LWIPIF_LWIP_IC_init, tcpip_input);
 
         /* Create bridge interface */
diff --git a/ethfw/apps/app_remoteswitchcfg_server/mcu_2_0/main.c b/ethfw/apps/app_remoteswitchcfg_server/mcu_2_0/main.c
index 75f18755..5cb4a469 100644
--- a/ethfw/apps/app_remoteswitchcfg_server/mcu_2_0/main.c
+++ b/ethfw/apps/app_remoteswitchcfg_server/mcu_2_0/main.c
@@ -214,7 +214,7 @@
 #define ETHAPP_BRIDGEIF_CPU_PORT_ID     BRIDGEIF_MAX_PORTS
 
 /* Inter-core netif IDs */
-#define ETHAPP_NETIF_IC_MCU2_0_MCU2_1_IDX   (0U)
+#define ETHAPP_NETIF_IC_MCU2_0_MCU3_0_IDX   (0U)
 #define ETHAPP_NETIF_IC_MCU2_0_A72_IDX      (1U)
 #define ETHAPP_NETIF_IC_MAX_IDX             (2U)
 
@@ -224,8 +224,8 @@
 /* Required size of the MAC address pool (specific to the TI EVM configuration):
  *  1 x MAC address for Ethernet Firmware
  *  2 x MAC address for mpu1_0 virtual switch and MAC-only ports (Linux, 1 for QNX)
- *  2 x MAC address for mcu2_1 virtual switch and MAC-only ports (RTOS)
- *  1 x MAC address for mcu2_1 virtual switch port (AUTOSAR) */
+ *  2 x MAC address for MCU3_0 virtual switch and MAC-only ports (RTOS)
+ *  1 x MAC address for MCU3_0 virtual switch port (AUTOSAR) */
 #define ETHAPP_MAC_ADDR_POOL_SIZE               (6U)
 
 /* Define A72_QNX_OS if A72 is running Qnx. Qnx doesn't load resource table. */
@@ -444,7 +444,7 @@ static EthFw_VirtPortCfg gEthApp_virtPortCfg[] =
         .portId       = ETHREMOTECFG_SWITCH_PORT_0,
     },
     {
-        .remoteCoreId = IPC_MCU2_1,
+        .remoteCoreId = IPC_MCU3_0,
         .portId       = ETHREMOTECFG_SWITCH_PORT_1,
     },
 #if defined(ENABLE_MAC_ONLY_PORTS)
@@ -453,7 +453,7 @@ static EthFw_VirtPortCfg gEthApp_virtPortCfg[] =
         .portId       = ETHREMOTECFG_MAC_PORT_1,
     },
     {
-        .remoteCoreId = IPC_MCU2_1,
+        .remoteCoreId = IPC_MCU3_0,
         .portId       = ETHREMOTECFG_MAC_PORT_4,
     },
 #endif
@@ -462,7 +462,7 @@ static EthFw_VirtPortCfg gEthApp_virtPortCfg[] =
 static EthFw_VirtPortCfg gEthApp_autosarVirtPortCfg[] =
 {
     {
-        .remoteCoreId = IPC_MCU2_1,
+        .remoteCoreId = IPC_MCU3_0,
         .portId       = ETHREMOTECFG_SWITCH_PORT_1,
     },
 };
@@ -486,13 +486,13 @@ static uint8_t gEthAppVringMemBuf[IPC_VRING_MEM_SIZE] __attribute__ ((section(".
 static uint32_t gEthAppRemoteProc[] =
 {
 #if defined(SOC_J721E)
-    IPC_MPU1_0, IPC_MCU1_0, IPC_MCU1_1, IPC_MCU2_1,
+    IPC_MPU1_0, IPC_MCU1_0, IPC_MCU1_1, IPC_MCU3_0,
     IPC_MCU3_0, IPC_MCU3_1, IPC_C66X_1, IPC_C66X_2,
     IPC_C7X_1,
 #elif defined(SOC_J7200)
-    IPC_MPU1_0, IPC_MCU1_0, IPC_MCU1_1, IPC_MCU2_1,
+    IPC_MPU1_0, IPC_MCU1_0, IPC_MCU1_1, IPC_MCU3_0,
 #elif defined(SOC_J784S4)
-    IPC_MPU1_0, IPC_MCU1_0, IPC_MCU1_1, IPC_MCU2_1,
+    IPC_MPU1_0, IPC_MCU1_0, IPC_MCU1_1, IPC_MCU3_0,
     IPC_MCU3_0, IPC_MCU3_1, IPC_MCU4_0, IPC_MCU4_1,
     IPC_C7X_1,  IPC_C7X_2,  IPC_C7X_3,  IPC_C7X_4,
 #endif
@@ -504,8 +504,8 @@ static struct netif netif_ic[ETHAPP_NETIF_IC_MAX_IDX];
 
 static uint32_t netif_ic_state[IC_ETH_MAX_VIRTUAL_IF] =
 {
-    IC_ETH_IF_MCU2_0_MCU2_1,
-    IC_ETH_IF_MCU2_1_MCU2_0,
+    IC_ETH_IF_MCU2_0_MCU3_0,
+    IC_ETH_IF_MCU3_0_MCU2_0,
     IC_ETH_IF_MCU2_0_A72
 };
 
@@ -1043,9 +1043,9 @@ static void EthApp_initNetif(void)
     NETIF_SET_CHECKSUM_CTRL(&netif, chksumFlags);
 #endif
 
-    /* Create inter-core virtual ethernet interface: MCU2_0 <-> MCU2_1 */
-    netif_add(&netif_ic[ETHAPP_NETIF_IC_MCU2_0_MCU2_1_IDX], NULL, NULL, NULL,
-              (void*)&netif_ic_state[IC_ETH_IF_MCU2_0_MCU2_1],
+    /* Create inter-core virtual ethernet interface: MCU2_0 <-> MCU3_0 */
+    netif_add(&netif_ic[ETHAPP_NETIF_IC_MCU2_0_MCU3_0_IDX], NULL, NULL, NULL,
+              (void*)&netif_ic_state[IC_ETH_IF_MCU2_0_MCU3_0],
               LWIPIF_LWIP_IC_init, tcpip_input);
 
     /* Create inter-core virtual ethernet interface: MCU2_0 <-> A72 */
@@ -1066,7 +1066,7 @@ static void EthApp_initNetif(void)
     gEthApp_lwipBridgePortIdMap[IPC_MCU2_0] = ETHAPP_BRIDGEIF_CPU_PORT_ID;
 
     bridgeif_add_port(&netif_bridge, &netif_ic[0]);
-    gEthApp_lwipBridgePortIdMap[IPC_MCU2_1] = ETHAPP_BRIDGEIF_PORT1_ID;
+    gEthApp_lwipBridgePortIdMap[IPC_MCU3_0] = ETHAPP_BRIDGEIF_PORT1_ID;
 
     bridgeif_add_port(&netif_bridge, &netif_ic[1]);
     gEthApp_lwipBridgePortIdMap[IPC_MPU1_0] = ETHAPP_BRIDGEIF_PORT2_ID;
@@ -1087,7 +1087,7 @@ static void EthApp_initNetif(void)
 
 #if defined(ETHAPP_ENABLE_INTERCORE_ETH)
     netif_set_up(&netif);
-    netif_set_up(&netif_ic[ETHAPP_NETIF_IC_MCU2_0_MCU2_1_IDX]);
+    netif_set_up(&netif_ic[ETHAPP_NETIF_IC_MCU2_0_MCU3_0_IDX]);
     netif_set_up(&netif_ic[ETHAPP_NETIF_IC_MCU2_0_A72_IDX]);
     netif_set_up(&netif_bridge);
 #else
diff --git a/ethfw/apps/common/r5f_mpu_j721e_default.c b/ethfw/apps/common/r5f_mpu_j721e_default.c
index 1a3d40bf..d413e635 100644
--- a/ethfw/apps/common/r5f_mpu_j721e_default.c
+++ b/ethfw/apps/common/r5f_mpu_j721e_default.c
@@ -129,10 +129,10 @@ const CSL_ArmR5MpuRegionCfg  gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =
         .memAttr          = 4U,
     },
     {
-        /* Region 6 configuration: DDR_MCU2_1_IPC_ADDR as non-cache */
+        /* Region 6 configuration: DDR_MCU3_0_IPC_ADDR as non-cache */
         .regionId         = 6U,
         .enable           = 1U,
-        .baseAddr         = 0xA3000000,
+        .baseAddr         = 0xA4000000,
         .size             = CSL_ARM_R5_MPU_REGION_SIZE_1MB,
         .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
         .exeNeverControl  = 1U,
diff --git a/ethfw/apps/common/r5f_mpu_j721e_safertos.c b/ethfw/apps/common/r5f_mpu_j721e_safertos.c
index d868382a..924b6b6b 100644
--- a/ethfw/apps/common/r5f_mpu_j721e_safertos.c
+++ b/ethfw/apps/common/r5f_mpu_j721e_safertos.c
@@ -153,9 +153,9 @@ xMPU_CONFIG_PARAMETERS  gMPUConfigParms[CSL_ARM_R5F_MPU_REGIONS_MAX] =
         .ulSubRegionDisable     = mpuREGION_ALL_SUB_REGIONS_ENABLED,
     },
     {
-        /* Region 5 configuration: DDR_MCU2_1_IPC */
+        /* Region 5 configuration: DDR_MCU3_0_IPC */
         .ulRegionNumber         = 5U,
-        .ulRegionBeginAddress   = 0xA3000000,
+        .ulRegionBeginAddress   = 0xA4000000,
         {
             .ulexeNeverControl  = 1U,
             .ulaccessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
diff --git a/ethfw/apps/common/r5f_mpu_j784s4_default.c b/ethfw/apps/common/r5f_mpu_j784s4_default.c
index 4bcf4224..c2861235 100644
--- a/ethfw/apps/common/r5f_mpu_j784s4_default.c
+++ b/ethfw/apps/common/r5f_mpu_j784s4_default.c
@@ -129,10 +129,10 @@ const CSL_ArmR5MpuRegionCfg  gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =
         .memAttr          = 4U,
     },
     {
-        /* Region 6 configuration: DDR_MCU2_1_IPC_ADDR as non-cache */
+        /* Region 6 configuration: DDR_MCU3_0_IPC_ADDR as non-cache */
         .regionId         = 6U,
         .enable           = 1U,
-        .baseAddr         = 0xA3000000,
+        .baseAddr         = 0xA4000000,
         .size             = CSL_ARM_R5_MPU_REGION_SIZE_1MB,
         .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
         .exeNeverControl  = 1U,
diff --git a/ethfw/apps/common/r5f_mpu_j784s4_safertos.c b/ethfw/apps/common/r5f_mpu_j784s4_safertos.c
index d41780d0..c9a2be77 100644
--- a/ethfw/apps/common/r5f_mpu_j784s4_safertos.c
+++ b/ethfw/apps/common/r5f_mpu_j784s4_safertos.c
@@ -153,9 +153,9 @@ xMPU_CONFIG_PARAMETERS  gMPUConfigParms[CSL_ARM_R5F_MPU_REGIONS_MAX] =
         .ulSubRegionDisable     = mpuREGION_ALL_SUB_REGIONS_ENABLED,
     },
     {
-        /* Region 5 configuration: DDR_MCU2_1_IPC */
+        /* Region 5 configuration: DDR_MCU3_0_IPC */
         .ulRegionNumber         = 5U,
-        .ulRegionBeginAddress   = 0xA3000000,
+        .ulRegionBeginAddress   = 0xA4000000,
         {
             .ulexeNeverControl  = 1U,
             .ulaccessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
diff --git a/ethfw/ethfw/src/ethfw.c b/ethfw/ethfw/src/ethfw.c
index 3aa264ed..25756f4e 100644
--- a/ethfw/ethfw/src/ethfw.c
+++ b/ethfw/ethfw/src/ethfw.c
@@ -1063,7 +1063,7 @@ int32_t EthFw_initRemoteConfig(EthFw_Handle hEthFw)
     /* Enable server-to-client notify service */
     cfg.notifyServiceCpswType = gEthFwObj.enetType;
     cfg.notifyServiceRemoteCoreId[0] = IPC_MPU1_0;
-    cfg.notifyServiceRemoteCoreId[1] = IPC_MCU2_1;
+    cfg.notifyServiceRemoteCoreId[1] = IPC_MCU3_0;
 
     /* Set CPSW Proxy shared multicast config.
      * All parameters have already been checked. */
diff --git a/ethfw/ethfw_build_flags.mak b/ethfw/ethfw_build_flags.mak
index 3b7f3ff5..de01c222 100644
--- a/ethfw/ethfw_build_flags.mak
+++ b/ethfw/ethfw_build_flags.mak
@@ -14,12 +14,12 @@ BUILD_EMULATION_ARCH?=x86_64
 BUILD_CPU_MPU1?=no
 BUILD_CPU_MCU1_0?=no
 BUILD_CPU_MCU2_0?=yes
-BUILD_CPU_MCU3_0?=no
+BUILD_CPU_MCU3_0?=yes
 BUILD_CPU_C6x_1?=no
 BUILD_CPU_C6x_2?=no
 BUILD_CPU_C7x_1?=no
 BUILD_CPU_MCU1_1?=no
-BUILD_CPU_MCU2_1?=yes
+BUILD_CPU_MCU2_1?=no
 BUILD_CPU_MCU3_1?=no
 BUILD_SOC_LIST ?= J721E J7200 J784S4
 export BUILD_SOC_LIST
diff --git a/ethfw/ethremotecfg/client/src/cpsw_proxy.c b/ethfw/ethremotecfg/client/src/cpsw_proxy.c
index 057a10a9..59bfc3b6 100644
--- a/ethfw/ethremotecfg/client/src/cpsw_proxy.c
+++ b/ethfw/ethremotecfg/client/src/cpsw_proxy.c
@@ -1186,7 +1186,7 @@ static void CpswProxy_remoteDeviceInit(uint32_t masterCoreId,
 #ifdef QNX_OS
     System_printf("Remote device (core : mpu1_0) .....\r\n");
 #else
-    System_printf("Remote device (core : mcu2_1) .....\r\n");
+    System_printf("Remote device (core : mcu3_0) .....\r\n");
 #endif
 }
 
diff --git a/pdk_jacinto_08_06_00_31/packages/ti/drv/enet/enet_component.mk b/pdk_jacinto_08_06_00_31/packages/ti/drv/enet/enet_component.mk
index 848dc4cf..cd1d34fe 100644
--- a/pdk_jacinto_08_06_00_31/packages/ti/drv/enet/enet_component.mk
+++ b/pdk_jacinto_08_06_00_31/packages/ti/drv/enet/enet_component.mk
@@ -42,10 +42,10 @@ drvenet_RTOS_LIST       = $(DEFAULT_RTOS_LIST)
 drvenet_SOCLIST         = am65xx j721e j7200 j721s2 j784s4
 drvenet_BOARDLIST       = am65xx_evm am65xx_idk j721e_evm j7200_evm j721s2_evm j784s4_evm
 drvenet_am65xx_CORELIST = mpu1_0 mcu1_0
-drvenet_j721e_CORELIST  = mpu1_0 mcu1_0 mcu2_0 mcu2_1
+drvenet_j721e_CORELIST  = mpu1_0 mcu1_0 mcu2_0 mcu2_1 mcu3_0
 drvenet_j7200_CORELIST  = mpu1_0 mcu1_0 mcu2_0 mcu2_1
 drvenet_j721s2_CORELIST = mpu1_0 mcu1_0 mcu2_0 mcu2_1
-drvenet_j784s4_CORELIST = mpu1_0 mcu1_0 mcu2_0 mcu2_1
+drvenet_j784s4_CORELIST = mpu1_0 mcu1_0 mcu2_0 mcu2_1 mcu3_0
 
 # Temp SoC/board lists which excludes for libraries/apps which
 # are not enabled yet
diff --git a/pdk_jacinto_08_06_00_31/packages/ti/drv/enet/intercore/include/ic_ipc.h b/pdk_jacinto_08_06_00_31/packages/ti/drv/enet/intercore/include/ic_ipc.h
index a1aeb290..7c577f6c 100644
--- a/pdk_jacinto_08_06_00_31/packages/ti/drv/enet/intercore/include/ic_ipc.h
+++ b/pdk_jacinto_08_06_00_31/packages/ti/drv/enet/intercore/include/ic_ipc.h
@@ -64,7 +64,7 @@ extern "C" {
 #define ICETH_IPC_ENDPT_BASE        10
 #define ICETH_IPC_ENDPT_MCU2_0_R5   (ICETH_IPC_ENDPT_BASE + 1)
 #define ICETH_IPC_ENDPT_MCU2_0_A72  (ICETH_IPC_ENDPT_BASE + 2)
-#define ICETH_IPC_ENDPT_MCU2_1      (ICETH_IPC_ENDPT_BASE + 3)
+#define ICETH_IPC_ENDPT_MCU3_0      (ICETH_IPC_ENDPT_BASE + 3)
 #define ICETH_IPC_ENDPT_MAX         (ICETH_IPC_ENDPT_BASE + 4)
 
 #define ICETH_ENDPT_NAME_LEN_MAX    128
diff --git a/pdk_jacinto_08_06_00_31/packages/ti/drv/enet/intercore/include/ic_queue.h b/pdk_jacinto_08_06_00_31/packages/ti/drv/enet/intercore/include/ic_queue.h
index 401ad6ba..4ca793ce 100644
--- a/pdk_jacinto_08_06_00_31/packages/ti/drv/enet/intercore/include/ic_queue.h
+++ b/pdk_jacinto_08_06_00_31/packages/ti/drv/enet/intercore/include/ic_queue.h
@@ -66,10 +66,10 @@ extern "C" {
 /*! Maximum no. of IcQ_Node objects in a queue */
 #define ICQ_MAX_QUEUE_SIZE      (2048)
 
-/*! MCU2_0 to MCU2_1 TX queue */
-#define ICQ_MCU2_0_TO_MCU2_1    (0U)
-/*! MCU2_1 to MCU2_0 TX queue */
-#define ICQ_MCU2_1_TO_MCU2_0    (1U)
+/*! MCU2_0 to MCU3_0 TX queue */
+#define ICQ_MCU2_0_TO_MCU3_0    (0U)
+/*! MCU3_0 to MCU2_0 TX queue */
+#define ICQ_MCU3_0_TO_MCU2_0    (1U)
 /*! MCU2_0 to A72 TX queue */
 #define ICQ_MCU2_0_TO_A72       (2U)
 /*! A72 to MCU2_0 TX queue */
diff --git a/pdk_jacinto_08_06_00_31/packages/ti/drv/enet/lwipific/inc/bufpool.h b/pdk_jacinto_08_06_00_31/packages/ti/drv/enet/lwipific/inc/bufpool.h
index 064c213a..a6a95cd2 100644
--- a/pdk_jacinto_08_06_00_31/packages/ti/drv/enet/lwipific/inc/bufpool.h
+++ b/pdk_jacinto_08_06_00_31/packages/ti/drv/enet/lwipific/inc/bufpool.h
@@ -64,10 +64,10 @@ extern "C" {
 /*! Total size of the Ethernet frame in bytes */
 #define ETH_FRAME_SIZE      (ETH_MAX_PAYLOAD + VLAN_TAG_SIZE)
 
-/*! MCU2_0 buffer pool for MCU2_0->MCU2_1 interface */
+/*! MCU2_0 buffer pool for MCU2_0->MCU3_0 interface */
 #define BUFPOOL_MCU2_0_R5   (0)
-/*! MCU2_1 buffer pool */
-#define BUFPOOL_MCU2_1      (1)
+/*! MCU3_0 buffer pool */
+#define BUFPOOL_MCU3_0      (1)
 /*! A72 buffer pool */
 #define BUFPOOL_A72         (2)
 /*! MCU2_0 buffer pool for MCU2_0->A72 interface */
diff --git a/pdk_jacinto_08_06_00_31/packages/ti/drv/enet/lwipific/inc/lwip2enet_ic.h b/pdk_jacinto_08_06_00_31/packages/ti/drv/enet/lwipific/inc/lwip2enet_ic.h
index 30c341d1..a2a34d82 100755
--- a/pdk_jacinto_08_06_00_31/packages/ti/drv/enet/lwipific/inc/lwip2enet_ic.h
+++ b/pdk_jacinto_08_06_00_31/packages/ti/drv/enet/lwipific/inc/lwip2enet_ic.h
@@ -69,12 +69,12 @@ extern "C" {
 /*                                 Macros                                     */
 /* ========================================================================== */
 
-/*! Inter-core virtual driver object instance ID: MCU2_0->MCU2_1
- *  This instance is created on MCU2_0 to interface with MCU2_1 */
-#define IC_ETH_IF_MCU2_0_MCU2_1     0
-/*! Inter-core virtual driver object instance ID: MCU2_0->MCU2_1
- *  This instance is created on MCU2_1 to interface with MCU2_0 */
-#define IC_ETH_IF_MCU2_1_MCU2_0     1
+/*! Inter-core virtual driver object instance ID: MCU2_0->MCU3_0
+ *  This instance is created on MCU2_0 to interface with MCU3_0 */
+#define IC_ETH_IF_MCU2_0_MCU3_0     0
+/*! Inter-core virtual driver object instance ID: MCU2_0->MCU3_0
+ *  This instance is created on MCU3_0 to interface with MCU2_0 */
+#define IC_ETH_IF_MCU3_0_MCU2_0     1
 /*! Inter-core virtual driver object instance ID: MCU2_0->A72
  *  This instance is created on MCU2_0 to interface with A72
  *
diff --git a/pdk_jacinto_08_06_00_31/packages/ti/drv/enet/lwipific/src/lwip2enet_ic.c b/pdk_jacinto_08_06_00_31/packages/ti/drv/enet/lwipific/src/lwip2enet_ic.c
index fc18a09e..4c59c1cf 100755
--- a/pdk_jacinto_08_06_00_31/packages/ti/drv/enet/lwipific/src/lwip2enet_ic.c
+++ b/pdk_jacinto_08_06_00_31/packages/ti/drv/enet/lwipific/src/lwip2enet_ic.c
@@ -102,26 +102,26 @@ Lwip2EnetIc_Object gLwip2EnetIcObj[IC_ETH_MAX_VIRTUAL_IF];
 Lwip2EnetIc_Params gIcEnetParams[IC_ETH_MAX_VIRTUAL_IF]=
 {
     {
-        .instId             = IC_ETH_IF_MCU2_0_MCU2_1,
+        .instId             = IC_ETH_IF_MCU2_0_MCU3_0,
         .ownerId            = IPC_MCU2_0,
-        .txQId              = ICQ_MCU2_0_TO_MCU2_1,
-        .rxQId              = ICQ_MCU2_1_TO_MCU2_0,
+        .txQId              = ICQ_MCU2_0_TO_MCU3_0,
+        .rxQId              = ICQ_MCU3_0_TO_MCU2_0,
         .bufPoolId          = BUFPOOL_MCU2_0_R5,
         .reqEndPtId         = ICETH_IPC_ENDPT_MCU2_0_R5,
-        .remoteCoreId       = IPC_MCU2_1,
+        .remoteCoreId       = IPC_MCU3_0,
         .endPtName          = "ENDPT_ICETH_MCU2_0_R5",
-        .remoteEndPtName    = "ENDPT_ICETH_MCU2_1",
+        .remoteEndPtName    = "ENDPT_ICETH_MCU3_0",
         .macAddr            = {0x00,0x01,0x02,0x03,0x04,0x05},
     },
     {
-        .instId             = IC_ETH_IF_MCU2_1_MCU2_0,
+        .instId             = IC_ETH_IF_MCU3_0_MCU2_0,
         .ownerId            = IPC_MCU2_0,
-        .txQId              = ICQ_MCU2_1_TO_MCU2_0,
-        .rxQId              = ICQ_MCU2_0_TO_MCU2_1,
-        .bufPoolId          = BUFPOOL_MCU2_1,
-        .reqEndPtId         = ICETH_IPC_ENDPT_MCU2_1,
+        .txQId              = ICQ_MCU3_0_TO_MCU2_0,
+        .rxQId              = ICQ_MCU2_0_TO_MCU3_0,
+        .bufPoolId          = BUFPOOL_MCU3_0,
+        .reqEndPtId         = ICETH_IPC_ENDPT_MCU3_0,
         .remoteCoreId       = IPC_MCU2_0,
-        .endPtName          = "ENDPT_ICETH_MCU2_1",
+        .endPtName          = "ENDPT_ICETH_MCU3_0",
         .remoteEndPtName    = "ENDPT_ICETH_MCU2_0_R5",
         .macAddr            = {0x00,0x01,0x02,0x04,0x05,0x06},
     },
@@ -181,9 +181,9 @@ Lwip2EnetIc_Handle Lwip2EnetIc_open(uint32_t instId)
 
     hIcObj->selfCoreId = EnetSoc_getCoreId();
     
-    /* Only MCU2_0 and MCU2_1 supported for now */
+    /* Only MCU2_0 and MCU3_0 supported for now */
     Lwip2EnetIc_assert( (hIcObj->selfCoreId == IPC_MCU2_0) ||
-                (hIcObj->selfCoreId == IPC_MCU2_1) );
+                (hIcObj->selfCoreId == IPC_MCU3_0) );
 
     hIcObj->remoteCoreId = gIcEnetParams[instId].remoteCoreId;
     hIcObj->txQId        = gIcEnetParams[instId].txQId;
diff --git a/pdk_jacinto_08_06_00_31/packages/ti/drv/enet/soc/j7x/j721e/enet_soc.c b/pdk_jacinto_08_06_00_31/packages/ti/drv/enet/soc/j7x/j721e/enet_soc.c
index ac05a59b..8386bf9f 100644
--- a/pdk_jacinto_08_06_00_31/packages/ti/drv/enet/soc/j7x/j721e/enet_soc.c
+++ b/pdk_jacinto_08_06_00_31/packages/ti/drv/enet/soc/j7x/j721e/enet_soc.c
@@ -449,6 +449,22 @@ CpswSoc_Cfg gEnetSoc_cpsw9gSocCfg =
             .coreIntNum = CSLR_R5FSS0_CORE1_INTR_CPSW0_MDIO_PEND_0,
             .srcIdx     = ENET_SOC_DIRECT_INTR_SRCIDX_INVALID,
         },
+#elif defined(BUILD_MCU3_0)
+        {   /* EVNT_PEND - Event pending interrupt (CPTS) */
+            .intrId     = CPSW_INTR_EVNT_PEND,
+            .coreIntNum = CSLR_R5FSS1_CORE0_INTR_CPSW0_EVNT_PEND_0,
+            .srcIdx     = ENET_SOC_DIRECT_INTR_SRCIDX_INVALID,
+        },
+        {   /* STATS_PEND - Statistics pending interrupt */
+            .intrId     = CPSW_INTR_STATS_PEND0,
+            .coreIntNum = CSLR_R5FSS1_CORE0_INTR_CPSW0_STAT_PEND_0,
+            .srcIdx     = ENET_SOC_DIRECT_INTR_SRCIDX_INVALID,
+        },
+        {   /* MDIO_PEND - MDIO interrupt */
+            .intrId     = CPSW_INTR_MDIO_PEND,
+            .coreIntNum = CSLR_R5FSS1_CORE0_INTR_CPSW0_MDIO_PEND_0,
+            .srcIdx     = ENET_SOC_DIRECT_INTR_SRCIDX_INVALID,
+        },
 #elif defined(BUILD_MPU1_0)
         {   /* EVNT_PEND - Event pending interrupt (CPTS) */
             .intrId     = CPSW_INTR_EVNT_PEND,
@@ -1015,6 +1031,8 @@ uint32_t EnetSoc_getCoreId(void)
     coreId = IPC_MCU2_0;
 #elif defined(BUILD_MCU2_1)
     coreId = IPC_MCU2_1;
+#elif defined(BUILD_MCU3_0)
+    coreId = IPC_MCU3_0;
 #else
 #error "Enet J721E SOC: Core not supported!!"
 #endif
@@ -1628,6 +1646,8 @@ static uint32_t EnetSoc_getCoreDevId(void)
     coreDevId = TISCI_DEV_R5FSS0_CORE0;
 #elif defined(BUILD_MCU2_1)
     coreDevId = TISCI_DEV_R5FSS0_CORE1;
+#elif defined(BUILD_MCU3_0)
+    coreDevId = TISCI_DEV_R5FSS1_CORE0;
 #else
 #error "Enet J721E SOC: Core not supported!!"
 #endif
@@ -1685,7 +1705,7 @@ int32_t EnetSoc_mapPort2QsgmiiId(Enet_Type enetType,
 
     /* Translate portNum to QSGMII Id.
      * In QSGMII mode, first QSGMII main port used is QSGMII ID 0 and next  QSGMII ID 1.
-     * For example – if MAC port 0 and port 3 are configured in QSGMII mode. Port 0 is QSMII 0
+     * For example <96> if MAC port 0 and port 3 are configured in QSGMII mode. Port 0 is QSMII 0
      * and 3 QSGMII1. Software is transparent to this selection */
 
     status = EnetSoc_getQsgmiiCfg(enetType, instId,
-- 
2.17.1