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[FAQ] AM64x Profinet: Component Placement Recommendation for SITARA MPU Memory

Ashwani Goel
Mastermind 23060 points
Part Number: PROCESSOR-SDK-AM64X
Other Parts Discussed in Thread: SYSCONFIG

Hi,

Can you please recommend how should I perform memory placement of various SW components when using Profinet - TSN on the AM64x processor.

  • 0
    TI__Mastermind 23060 points

    Hi,

    This document explains the MCU+ SDK and Profinet component placement recommendation on different memory controller (DDR/MSMC/TCM) for Sitara AM64x platform.

    • Component placement

    Component Sub Component Description Alignment MPU Settings Section Comments
    ENET ENET_DMA_RING_M
    EMPOOL    		 This is DMA ring accelerator
    memory pool. Each ring
    contains four memory
    spaces on the VBUSM target bus for access, each of which
    is 512 bytes long, with a total
    of 4 kB per ring. Each ring
    space starts immediately
    after the preceding ring.    		 128U -
    Cache
    alignm
    ent    		 Cacheable: 1
    Bufferable: 1
    Shareable: 0    		 .bss Note: the memory alignment described here is the default configuration and part of sysconfig generated file ti_enet_config.c. Refer below  macro.
    ENETDMA_CACHELINE_ALIGNMENT
    UDMA_CACHELINE_ALIGNMENT
    ENET_DMA_DESC_M
    EMPOOL    		 This is DMA descriptor
    memory pool.    		 32U -
    Cache
    alignm
    ent    		 Cacheable: 1
    Bufferable: 1
    Shareable: 0    		 .bss This subcomponent can be placed in MSMC/DDR target memory and MPU settings should be strictly followed.
    ENET_DMA_PKT_ME
    MPOOL    		 Large/medium/small packet
    memory pools. This is
    application packet memory
    pool contains actual eth
    packets.    		 32U -
    Cache
    alignm
    ent    		 Cacheable: 1
    Bufferable: 1
    Shareable: 0    		 .bss
    ICSSG Firmware - icssfw ICSSG Firmware headers - for
    switch and DUAL MAC    		 128U Cacheable: 1
    Bufferable: 1
    Shareable: 0    		 .rodata This subcomponent has to be placed in MSMC target memory.
    host buffer pool Host buffer pool memory

    64U

    Cacheable: 1
    Bufferable: 1
    Shareable: 0

    >> NOLOAD

    		 .bss Note: the memory alignment described here is the default configuration and part of sysconfig generated file ti_enet_config.c Refer below macro:
    ICSSG_CACHELINE_ALIGNMENT
    This subcomponent has to be placed
    in MSMC target memory.
    host queue memory
    pool    		 Host egress queue memory

    64U

    Cacheable: 1
    Bufferable: 1
    Shareable: 0

    >> NOLOAD

    		 .bss Note: the memory alignment described here is the default configuration and part of sysconfig generated file ti_enet_config.c Refer below macro:
    ICSSG_CACHELINE_ALIGNMENT
    This subcomponent has to be placed
    in MSMC target memory.
    Port buffer pool Port buffer pool memory

    64U

    Cacheable: 1
    Bufferable: 1
    Shareable: 0

    >> NOLOAD

    		 .bss Note: the memory alignment described here is the default configuration and part of sysconfig generated file ti_enet_config.c Refer below macro:
    ICSSG_CACHELINE_ALIGNMENT. This subcomponent has to be placed
    in MSMC target memory.
    Scratch buffer Scratch buffer used for error
    and large size frames.

    64U

    Cacheable: 1
    Bufferable: 1
    Shareable: 0

    >> NOLOAD

    		 .bss Note: the memory alignment described here is the default configuration and part of sysconfig generated file ti_enet_config.c Refer below macro: ICSSG_CACHELINE_ALIGNMENT. This subcomponent has to be placed in MSMC target memory.
    Profinet - PPM
    buffers    		 PPM buffer and
    TRPD list    		 PPM buffers - application
    buffer for storing IO data.
    PPM TRPD list - BCDMA block
    copy transfer request
    descriptors

    128U

    Cacheable: 1
    Bufferable: 1
    Shareable: 0

    >> NOLOAD

    		 .bss PPM buffers = Max AR * Max PPM buffer size
    Refer: rt_msmc_mem in linkercmd file
    freeRTOS Boot code GROUP: hwi, cache, mpu,
    boot: freeRTOS IRQ handlers,
    hardware interrupt module
    and boot code

    8

    Cacheable: 1
    Bufferable: 1
    Shareable: 0

    		 .text
    R5F entry table and
    vector    		 R5F HWIP

    8

    Cacheable: 1
    Bufferable: 1
    Shareable: 0

    		 .vectors
    ARM IRQ, FIQ, SVC,
    ABORT and
    UNDEFINED stack    		 GROUP: All the arm r5f
    stacks for different modes

    8

    Cacheable: 1
    Bufferable: 1
    Shareable: 0
    SBL

    Boot loader: 0-512KB (2
    Banks) of MSMC is occupied
    Refer: https://softwaredl.ti.com/mcu-plus-sdk/esd/AM64X/latest/exports/docs/
    api_guide_am64x/MEMORY_MAP.htm

    		 -

    		In this bank .text or .rodata cannot be placed. Otherwise, this region can also be used for application stack, heap or firmware buffers (refer ICSSG component and buffer pool sub component)

    Rest of code,

    initialized/uninitialized data,

    uninitialized global variables,

    		 GROUP: All the un-initialized
    global variables

    8

    Cacheable: 1
    Bufferable: 1
    Shareable: 0

    		 .bss

    These subcomponents can be placed in MSMC/DDR target memory and MPU settings should be strictly followed.

    		GROUP: Heap and stack

    8

    Cacheable: 1
    Bufferable: 1
    Shareable: 0

    .system

    .stack
    GROUP: Text and read only
    data

    8

    Cacheable: 1
    Bufferable: 1
    Shareable: 0

    .text

    .rodata
    GROUP: data - initialized
    data

    8

    Cacheable: 1
    Bufferable: 1
    Shareable: 0

    .data
    • Memory region reservation
    Memory Region Name Region Start Length MPU Settings Description
    MSRAM (Multicore Shared Memory Controller) MSMC_cached 0x70000000 0x1e0000 Cacheable: 1
    Bufferable: 1
    Shareable: 0
    MSMC_uncached 0x701e0000 0x0C0000 Cacheable: 0
    Bufferable: 1
    Shareable: 1
    DDR4 DDR_cached 0x86000000 0x01800000 Cacheable: 1
    Bufferable: 1
    Shareable: 0
    DDR_uncached 0x87800000 0x00400000 Cacheable: 0
    Bufferable: 1
    Shareable: 1
    Flash 0x60100000 0x80000 Cacheable: 1
    Bufferable: 1
    Shareable: 1    		 This section can be used to put XIP section
    of the application in flash, make sure this
    does not overlap with other CPUs. Also
    make sure to add a MPU entry for this
    section and mark it as cached and code
    executable.
    Note: This memory is not used in PN TSN
    application - TI unit test.
    R5F TCM R5F_VECS 0x00000000 0x00000040 Cacheable: 1
    Bufferable: 1
    Shareable: 0
    R5F_TCMA 0x00000040 0x00007FC0 Cacheable: 1
    Bufferable: 1
    Shareable: 0
    R5F_TCMB0 0x41010000 0x00008000 Cacheable: 1
    Bufferable: 1
    Shareable: 0

    Best Regards