Currently the GPMC multiple read/write is not working, any advice? GPMC single read/write is working. We are trying to get GPMC multiple read to work first.
- NOR Flash like, asynchronous and synchronous devices - Non-multiplexed attached dev…
Hidekazu said: Regarding the GPMC_CLK not being output correctly, we have confirmed that the expected clock is being output by setting GPMCFCLKDIVIDER. (However, the damping resistor needs to be adjusted.)
Good to hear the progress…
Other Parts Discussed in Thread: CLOCKTREETOOL Hi, Experts
We are considering how to operate GPMC_CLK=100MHz while keeping the DSP/ARM clock at 1000Mhz using ClockTreeTool. The current design is to input 24MHz to SYSOSC and SYSCLK1=1000MHz with PLL_MAIN…
Other Parts Discussed in Thread: 66AK2G12 Hi,Experts
In page 1202, Table 7-127 of the 66AK2G12 data sheet (spruhy8i) The DDR on the evaluation board has a Row Address of 16bits, but the DDR on the custom board has a Row Address of 15bits.
Can the 66AK2G12…
Part Number: 66AK2G12 We have a successful 600 MHz design that we would like to migrate to 1000 MHz. Is there a comprehensive migration guide?
What are the required changes? Hardware voltages/bootloader PLL initialization, DDR clocks?
I found the following thread which seems to be the same phenomenon. Are these measures effective?
66AK2G12: POR doesn't work e2e.ti.com/.../66ak2g12-por-doesn-t-work
- Last Thread - I think I found the reason why POR does not working. The pin…