Part Number: 66AK2H12 Hi
I want t to integrate SRIO and NDK for 66AK2h12. I set event ID 49 for SRIO so I must set "QM Interrupt" for it so according to 66AK2h12 datasheet as below:
Q1:
Should I set QMSS_INT 8,9,10 and 11?
In the configuration…
Part Number: 66AK2H12 Hi,
Customer clear TIMHIRS and TIMLORS, but TSTAT_LO and TSTAT_HI are not reset to 0.
3.6 Timer Reset Sources
https://www.ti.com.cn/cn/lit/ug/sprugv5a/sprugv5a.pdf
TImer mode is dual 32bit unchain mode. Is there a demo available…
Part Number: 66AK2H12 Hi
MCSDK: 3.1.4.7
CCS: 7
OS: win7
I could drive SRIO and NDK on C6678 before, SRIO and NDK worked simultaneously on my C6678 project correctly.
I want to drive SRIO and NDK on 66AK2H12 too, I implement SRIO and NDK driver…
Part Number: 66AK2H12 Other Parts Discussed in Thread: 66AK2H06 , 66AK2H14 How to build U-Boot from "Processor-SDK-Linux" for K2H Family devices (EVMK2H, 66AK2H12, 66AK2H06, 66AK2H14 )?
HI
Thanks for the reply
1.Before only I searched for 66ak2h12 documents, I didn't find any related document about flashing.
2. I saw that link in the e2e forum but that didn't helped me.
please give procedure for flashing .
Thanks and regards…
Part Number: 66AK2H12 Other Parts Discussed in Thread: 66AK2H14 , , 66AK2H06
How to build Boot Monitor, Linux, Device tree, and Kernel from "Processor-SDK-Linux" for K2H Family devices (EVMK2H, 66AK2H12, 66AK2H06, 66AK2H14)?
Hi,
You CCS memory view is with L1D cache and L2 cache checked in the box. So what you saw is in the cache, not in the MSMC memory. You can uncheck those two boxes to understand the difference between cached memory and uncached memory.
In core A,…
Added few more FAQs for Keystone I and II
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I2C boot parameter table correction
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1201776/faq-66ak2h14-i2c-boot-parameter-table…
