Part Number: ADC12DJ1600-Q1 Hello,
We are rapidly moving forward with a new PCB design with the TI ADC12xJ1600-Q1 which requires a new register configuration and JESD interface IP for our Ultrascale+ MPSOC to support both 2 and 4 channel modes.
We…
Part Number: ADC12DJ5200RF-DESIGN Other Parts Discussed in Thread: ADC12DJ1600 , ADC12QJ1600 Hello, sorry I put a different part number of the "TI part number" box in this forum since your system doesn't show ADC12DJ1600 and did not allow me to move forward…
Part Number: ADC12DJ1600 Other Parts Discussed in Thread: ADC12DJ5200RF Tool/software: Hi,
we need to adjust per channel the gain and offset of the converter, but there is insufficient information in the specification to
explain the relationship between…
Part Number: ADC12DJ1600 Other Parts Discussed in Thread: ADC12QJ1600 Tool/software: (L) Hi,
I would like to configure the dual core ADC12DJ1600 in JMODE9, but only use the first core.
How should the FPGA IP be configured to support this? Especially…
Part Number: ADC12DJ1600 Tool/software: Hi guys,
I am trying to build the ref design ZCU102_64b66b included in the latest version of TI204C-IP, but I get an error saying that the IP is considered a blackbox, so no success yet:
I am running Vivado…
Part Number: ADC12DJ1600-Q1 TI team,
Does ADC12DJ1600-Q1 device support any function that could be used for detecting loss of messages on the SPI interface between the ADC12DJ1600-Q1 ADC and FPGA Controller?
Do you know how this is done in typpical…
Part Number: ADC12DJ1600-Q1 Team,
Question is about Code Error Rate (CER) mentioned in the datasheet.
In the datasheet is only mentioned what CER is and vwhat value is for this.
Is there any possibility we can monitor this CER? I mean if the…
Part Number: ADC12DJ1600-Q1
Hello,
My colleagues and I are looking for some trigger conditions for background calibration. We vaguely do understand how it can be done, mainly by setting different fixed temperatures. I was wondering if you have any…
Part Number: ADC12DJ1600 Hi,
I want to know can I change the lane ordering(making any physical lane as logical lane 0 and so on) for JESD204C.
I can see there is one register DID which is mentioned in Table 9-18 for lane assignment in the datasheet…
