Because of the Thanksgiving holiday in the U.S., TI E2E™ design support forum responses may be delayed from November 25 through December 2. Thank you for your patience.
Part Number: ADC12DJ1600-Q1 TI team,
Does ADC12DJ1600-Q1 device support any function that could be used for detecting loss of messages on the SPI interface between the ADC12DJ1600-Q1 ADC and FPGA Controller?
Do you know how this is done in typpical application…
Part Number: ADC12DJ1600-Q1
Hello,
My colleagues and I are looking for some trigger conditions for background calibration. We vaguely do understand how it can be done, mainly by setting different fixed temperatures. I was wondering if you have any recommendations…
Part Number: ADC12DJ1600-Q1 Team,
Question is about Code Error Rate (CER) mentioned in the datasheet.
In the datasheet is only mentioned what CER is and vwhat value is for this.
Is there any possibility we can monitor this CER? I mean if the HS ADC happens…
Part Number: ADC12DJ1600 Hi,
I want to know can I change the lane ordering(making any physical lane as logical lane 0 and so on) for JESD204C.
I can see there is one register DID which is mentioned in Table 9-18 for lane assignment in the datasheet. But…
Hi Nandini,
No plans at this time to NRND this device. If you do want to consider newer devices we have the ADC12DJ1600 , ADC12DL1500 or ADC12DL2500 available.
