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Interface

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Interface forum

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Texas Instruments (TI) Interface support forum is an extensive online knowledge base where millions of technical questions and solutions are available 24/7. You can search interface IC content or ask technical support questions on everything from ESD protection to interfacing with USB, Ethernet, and HDMI. Find the right solution for your circuit design challenges by using our TI E2E™ support forums that are supported by thousands of contributing TI experts.
Frequent questions
  • [FAQ] DP83822IF: Fiber Link Status

    Alvaro (Al-vuh-roe) Reyes
    Alvaro (Al-vuh-roe) Reyes
    Part Number: DP83822IF Other Parts Discussed in Thread: DP83822HF , The DP83822IF and DP83822HF are the fiber capable variants of the DP83822. Bit 2 in Register 0x0001 indicates link status for both Copper and Fiber modes of operation. In copper mode, this…
    • 3 days ago
    • Interface
    • Interface forum
  • [FAQ] Extended Register Space Access for Ethernet PHYs

    Alvaro (Al-vuh-roe) Reyes
    Alvaro (Al-vuh-roe) Reyes
    Our Ethernet PHYs have a standard set of registers, 0x0-0x1F, that can be accessed in a straight forward fashion. Registers beyond 0x1F require a different approach to access. This FAQ is intended to provide a few examples on how to read/write these registers…
    • 8 days ago
    • Interface
    • Interface forum
  • [FAQ] SN65DSI86: SN65DSI86 Resolution Guide

    Allison Noe
    Allison Noe
    Part Number: SN65DSI86 What display resolution will the SN65DSI86 support?
    • Answered
    • 15 days ago
    • Interface
    • Interface forum
  • [FAQ] DP83867E: What is the default mode of RGMII when using DP83867, shift or align?

    Gerome Cacho
    Gerome Cacho
    Part Number: DP83867E When bootstrapped to be in RGMII mode, DP83867 will be in shift mode by default; not align mode. The modes will be corroborated via Reg 0x32[1:0].
    • 21 days ago
    • Interface
    • Interface forum
  • [FAQ] DP83869HM: How to generate 125MHz on CLKOUT pin for DP83869

    Gerome Cacho
    Gerome Cacho
    Part Number: DP83869HM DP83869HM needs an additional register to be written to enable CLKOUT modification. By default, this signal is a buffered version of the XI signal. Reg 0xC6 must have 0x10 written in order for the value in Reg 0x170[12:8] to take…
    • 21 days ago
    • Interface
    • Interface forum
  • [FAQ] TI Ethernet PHY Capacitive Coupling (Transformerless Operation)

    Alvaro (Al-vuh-roe) Reyes
    Alvaro (Al-vuh-roe) Reyes
    Other Parts Discussed in Thread: DP83869 , DP83825 Summary: All of our Industrial Ethernet PHYs support Transformer-less Operation via Capacitive Coupling except for the DP83867. The DP83867 does not support Transformer-less Operation. List of Industrial…
    • 23 days ago
    • Interface
    • Interface forum
  • [FAQ] DP83867E: Ethernet PHY SGMII Vdiff Upper and Lower Input Limits

    Alvaro (Al-vuh-roe) Reyes
    Alvaro (Al-vuh-roe) Reyes
    Part Number: DP83867E Other Parts Discussed in Thread: DP83869 The DP83867 and DP83869 both have the same Vdiff Upper and Lower Input Limits of: 100 mV and 800 mV
    • 1 month ago
    • Interface
    • Interface forum
  • [FAQ] What capacitance should my ESD diode be?

    Ethan Sempsrott
    Ethan Sempsrott
    Other Parts Discussed in Thread: ESD2CANXL24-Q1 , ESD2CAN24-Q1 , ESD2CANFD24-Q1 , ESD122 What should be considered when selecting a diode with parasitic capacitance?
    • Answered
    • 1 month ago
    • Interface
    • Interface forum
  • [FAQ] DP83825I: How to adjust the Output Differential Voltage (VOD) of the DP83825I

    David Creger
    David Creger
    4540.DP83825I VOD Adjustment.pptx
    • 2 months ago
    • Interface
    • Interface forum
  • [FAQ] DP83TG720R-Q1: Why is my SGMII eye measurement distorted?

    Melissa Chang
    Melissa Chang
    Part Number: DP83TG720R-Q1 SGMII signal is high frequency low-voltage differential signal. Both layout design and measurements need to be accurate for good eye diagram capture. Common board design guidelines: 100ohms+/-10% differential traces, ac-coupling…
    • 2 months ago
    • Interface
    • Interface forum
>

View FAQ threads
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  • Not Answered

    [FAQ] TI Ethernet PHY Capacitive Coupling (Transformerless Operation) 0

    274 views
    0 replies
    Started 23 days ago
    by Alvaro (Al-vuh-roe) Reyes
  • Not Answered

    [FAQ] DP83867E: Ethernet PHY SGMII Vdiff Upper and Lower Input Limits 0

    212 views
    0 replies
    Started 1 month ago
    by Alvaro (Al-vuh-roe) Reyes
  • Not Answered

    [FAQ] DP83867E: How to force 10/100/1000 Mbps speed in Ethernet PHYs? 0

    1698 views
    0 replies
    Started 10 months ago
    by Evan Mayhew
  • Not Answered

    [FAQ] DP83TG720S-Q1: How to read or write registers in extended register space of Ethernet PHY? 0

    2152 views
    0 replies
    Started over 1 year ago
    by Vikram Sharma
  • Not Answered

    [FAQ] DP83867CR: How to generate recovered clock using DP83867? 0

    1717 views
    0 replies
    Started over 1 year ago
    by Vikram Sharma
  • Not Answered

    [FAQ] ESD and TVS Protection Devices: Key Collateral and FAQs 0

    4908 views
    0 replies
    Started over 1 year ago
    by Matt Smith3
  • Not Answered

    [FAQ] Transceiver FAQs 0

    3042 views
    0 replies
    Started over 1 year ago
    by Chris Ayoub
  • Not Answered

    [FAQ] DP83867E: What is the default mode of RGMII when using DP83867, shift or align? 0

    137 views
    0 replies
    Started 21 days ago
    by Gerome Cacho
  • Not Answered

    [FAQ] DP83869HM: How to generate 125MHz on CLKOUT pin for DP83869 0

    133 views
    0 replies
    Started 21 days ago
    by Gerome Cacho
  • Not Answered

    [FAQ] DP83826E: How does Strap1 (CLKOUT/LED1) work on DP83826? 0

    154 views
    0 replies
    Started 4 months ago
    by Gerome Cacho
  • Answered

    [FAQ] TPS65987D: New USB Type C PD 3.1 Spec enables Extended Power Range up to 240W (EPR) 0

    9007 views
    6 replies
    Latest 6 months ago
    by Eric Beljaars
  • Not Answered

    [FAQ] What different types of Reset are available on a TI Ethernet PHY? 0

    1881 views
    0 replies
    Started 10 months ago
    by David Creger
  • Not Answered

    [FAQ] DP83TC812S-Q1: How to disable 25MHz clock on clkout pin? 0

    1524 views
    0 replies
    Started 11 months ago
    by Vikram Sharma
  • Not Answered

    [FAQ] Which conformal coating is recommended for Ethernet PHY products? 0

    1510 views
    0 replies
    Started 11 months ago
    by Vikram Sharma
  • Not Answered

    [FAQ] DP83867IR: How to test the link-quality using DP83867's BIST and status registers? 0

    1560 views
    0 replies
    Started 11 months ago
    by Vikram Sharma
  • Not Answered

    [FAQ] DP83TD510E: How to check throughput without depending upon MAC? 0

    1453 views
    0 replies
    Started 11 months ago
    by Vikram Sharma
  • Not Answered

    [FAQ] DP83826E: In enhanced mode, how does DP83826 strapping work? 0

    1803 views
    0 replies
    Started over 1 year ago
    by Gerome Cacho
  • Answered

    [FAQ] TPS25750: How do I create a Sink-Only USB-C PD port to replace a legacy Barrel Jack Connector? 0

    6170 views
    1 reply
    Latest over 2 years ago
    by Chuck Branch
  • Not Answered

    [FAQ] DS90UB953-Q1: Latency of DS90UB953-Q1 and DS90UB954-Q1 0

    5007 views
    2 replies
    Latest over 3 years ago
    by Neta Sherer
  • Suggested Answer

    SN65HVD1050: SN65HVD1050 data sheet change esd parameter value 0

    78 views
    6 replies
    Latest 6 hours ago
    by Marco Pivetti
>
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