Part Number: ADC12DJ1600-Q1 Hello,
We are rapidly moving forward with a new PCB design with the TI ADC12xJ1600-Q1 which requires a new register configuration and JESD interface IP for our Ultrascale+ MPSOC to support both 2 and 4 channel modes.
We…
Part Number: ADC12DJ1600-Q1 TI team,
Does ADC12DJ1600-Q1 device support any function that could be used for detecting loss of messages on the SPI interface between the ADC12DJ1600-Q1 ADC and FPGA Controller?
Do you know how this is done in typpical…
Part Number: ADC12DJ1600-Q1 Team,
Question is about Code Error Rate (CER) mentioned in the datasheet.
In the datasheet is only mentioned what CER is and vwhat value is for this.
Is there any possibility we can monitor this CER? I mean if the…
Part Number: ADC12DJ1600-Q1
Hello,
My colleagues and I are looking for some trigger conditions for background calibration. We vaguely do understand how it can be done, mainly by setting different fixed temperatures. I was wondering if you have any…
Part Number: ADC12DJ1600-Q1 Other Parts Discussed in Thread: HD3SS3411-Q1 , HD3SS3411 Team,
Customer is trying to validate the ADC12DJ1600-Q1 and in order to do that theyalso have to measure the switching time for the MUX.
Below is a screenshot of…
Jimmy,
The schematic is attached. FYI, you can download the entire board design package including the schematic under the ADC12DJ3200EVM product folder on the TI website.
Regards,
Jim
6874.ADC12DJ3200_HSP001EVM-SCH_A.pdf
HSP001-001EVM_A-SCH.pdf Sepeedah,
On the EVM, the customer would install R180, R179, R151, and R162, and remove R1, R4, R6, and R9. This would allow them to bring in a differential DC coupled signal on SMA J1 and J3 for channel A, and SMA J4 and J6…
Hi Apurva
1. The 6.4 GSPS sample rate is achieved using JMODEs 0, 1, 4, 5 and 17. In these modes the single ADC input is sampled on both rising and falling edges of the input CLK.
2. The ADC can be driven with DC-coupled inputs by removing R1 and…
