Part Number: ADC34J24EVM Other Parts Discussed in Thread: ADC34J24 , LMK04828 Hi,
I am evaluating ADC34J24EVM connected with ZCU102 Xilinx FPGA board.
I suceeded accessing ADC34J24 registers through FMC from ZCU102 SPI.
But I failed with LMK04828 SPI read…
Part Number: ADC34J24 Other Parts Discussed in Thread: TI-JESD204-IP , Hi Experts.
I am evaluating ADC34J24EVM + Xilinx ZCU102 FPGA board with TI-JESD204-IP.
What is the maximum "K" value available in ADC34J24?
I think TX K and RX K value should…
Part Number: ADC34J24 Hi Experts,
Good Day
I hope you're doing fine. I need your help. One of our customers is asking below setting.
Question 1) If K=8 in the FRAMES PER MULT IFRAME field of register 31, does the LMFC count range from 0 to 8, and when…
Part Number: ADC34J24 My customer is working to drive the differential input circuit on the ADC34J24, with a schematic similar to Figure 202 in the datasheet. The Vcm output pin is at the 0.95V nominal level noted in the datasheet. He would like to provide…
Part Number: ADC34J24EVM Other Parts Discussed in Thread: ADC34J24 , LMK04828 Hi,
I am trying to do SPI communication with ADC34J24 and LMK04828 via FMC using ZCU102 Xilinx FPGA board.
I have couple of questions?
1. Can I have FPGA Source code for 5M80ZT100…
Part Number: ADC34J24EVM Other Parts Discussed in Thread: ADC34J24 , I have TI204C-IP and plannig to use ADC34J24 with Xilinx MpSoC+.
I'd like test the FPGA IP before my custome hardware come out.
My plan is using ADC34J24EVM and Xilinx ZCU102 EVB.
…
Part Number: 66AK2L06 Other Parts Discussed in Thread: ADC34J24 , ADC3424 , Hi,
Do we have DSP with LVDS or JESD204B port that is compatible for ADC3424/ADC34J24?
Customer is having hard time using the FPGA.
Thank you.
Regards, May
Part Number: ADC3424 Other Parts Discussed in Thread: ADC34J24 , Hi,
Do we have MCU/DSP MCU or DSP with LVDS or JESD204B port that is compatible for ADC3424/ADC34J24?
Customer is having hard time using the FPGA.
Thank you.
Regards, May
Hi Hiroshi,
Question 1)
It is recommended to AC couple SYSREF since SYSREF has an internal DC bias of 0.9V. It is ok that it is a pulse (one-shot) since it should be a signal in MHz range.
Question 2)
The EVM is using LVPECL to maximize the signal swing…