Part Number: ADS127L18
Hello,
I am working on a test PCB that uses three ADS127L18 ADCs connected in daisy‑chain mode , and I would like to request a review of my schematic to ensure the digital and clocking connections are correct before moving…
Part Number: ADS127L18 Other Parts Discussed in Thread: ADS127L11 , TEST2 I am attempting to control the ADS127L18 using an FPGA to sample 8-lane data.
The intended configuration is as follows: WideBand OSR=32, external CLK 32.768 MHz, reading from…
Part Number: ADS127L18 Other Parts Discussed in Thread: ADS1278-HT Hello,
I am testing ADS127L18 at temperature and it works well up to ~ 175C. At around that temperature I noticed the voltage on pin CAPA drops from ~-1V to -2.5V. And it keeps cycling…
Part Number: ADS127L18 Hi,
I have a ADS127L18 on a board using the hardware programming. Mode is set to MAX speed. However the clock is a 25.6MHz clock.
What is the expected output frequency and Sinc4+Sinc1 Filter Performance in this configuration…
Part Number: ADS127L18 Hello,
I am using several FPGA/ADC pairs, distant from each other. The FPGAs have the same source clock, from which they derive their own slower CLKIN.
I have to synchronize both START and CLKIN between ADCs. The CLKIN synchronization…
Part Number: ADS127L18
Hi team,
On the ADS127L18EVM, pull-up resistors of 100 kohm are connected as shown in the schematic.
We were concerned that 100 kohm might be too large, so we previously changed the pull-up resistor on the MODE pin to…
Part Number: ADS127L18 Tool/software: Hello Keith,
is it possible to order PADS127L18IRSHR as sample already now directly from TI?
We would need 2-3 pcs. desparately and very soon. Our design is ready and tested and the
project time line is very…
Part Number: ADS127L18 Hello,We have a question regarding the timing requirements of the START signal in the ADS127L18.In our system, the START signal is generated by an FPGA, while the ADC clock is provided either by the internal oscillator of the ADS127L18…
Part Number: ADS127L18 Tool/software: Hello
Section 7.4.10.1 of the datasheet says:
In hardware control mode, there is no access to the STATUS register, therefore an error is only caused by the ADC_ERR bit. Reset or power-cycle the ADC to clear an…
