Part Number: ADS41B49EVM I am interfacing an ADS41B49EVM to a Zedboard (Zynq-7020) with the FMC-ADC-ADAPTER. I am looking for any reference HDL for interfacing to the parallel DDR LVDS outputs of the ADS41B49 (or something similar). Thank you!!
Part Number: ADS41B49EVM Hello,
I am interested in evaluating ADS41B49 for a single ended input signal.
From the eval board datasheet it seems it can only accept differential inputs, is there any way to use single ended input?
Regards,
Mahmoud
Part Number: ADS41B49EVM I have two hardware，one is the ADS41B49EVM,and the other one is TSW1405EVM. I have already installed ADC SPI and HSDC GUI. However, I give clock (20Mhz , Vp-p1.5V )and give sine wave(50Mhz, 1dbm ) to J6, I can't see anything on…
Hello,
I am hoping to interface the cyclone V with a ADS41B49EVM, is there any example code that exists for this purpose? If not, could someone lay out or point me to a good reference on what the idea behind this would be?
Cheers,
Kyle
Hi Reza
The DEV-ADC34j22 module has a JESD204B high speed serial data interface, and for that reason is not compatible with the DE2-115 development board.
So your options are to either get a different capture/development board that is compatible with…
Hi Hamid,
From what I see here: http://www.ti.com/tool/ads41b49evm#Technical Documents it seems that this ADC is mainly intended to be interfaced to FPGAs. There is a capture board mentioned in the EVM user guide: https://estore.ti.com/TSW1200EVM-TSW1200…
Kyle,
The clocking speed refers to the clock provided to the clock input. This is the "sampling rate" of the ADC. The ADS41B49 can sample up to 250 MSPS (Milliion samples per second). So, the ADS41B49 should be able to handle a clock speed of 250 MHz…
Other Parts Discussed in Thread: ADS41B49 , ADS4249EVM , ADS4249 Hello:
I'm interested in the TI ADS41B49 device and am wondering if it is set up to be able to evaluate this device with the EVM:
http://www.ti.com/tool/ads41b49evm
and the TI HSMC to Altera…
