Part Number: AM3352 hi Sir
I follow the BBB platform (use AD3352 ) to do the HMI , need reboost many times ,then the system work correct
but loss power about one hour, re boot the system , can't work correct,did you have any advise?
SOC(AM3352ZCZ…
Part Number: AM3352 Hi,
Q1. When we asked a crystal oscillator manufacturer to match a custom board, we were told that the optimal load capacitance on the board would be 27p to 30pF. According to the data sheet, the maximum load capacitance is 24pF. The…
Part Number: AM3352 Other Parts Discussed in Thread: AM3358 Hi
May I have question about AM3352?
On this topic, https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1106327/am3358-migration-to-am3352
I think that Linux had build for…
Part Number: AM3352 Hi Expert,
TI spl init sequence:
... sdram_init(); // write ddr parameter into register
//read/write ddr3 to verify ddr3 size,but some ddr3 will fail at this step when mass production,
//read back value is not same as write value, …
Part Number: AM3352 Other Parts Discussed in Thread: AMIC110 Hi experts
My customer currently uses [SCR.TXEMPTYCTLIT=1] for UART FIFO EMPTY interrupt. However, according to actual measurements, in the case of high baud rate transmission, there is a very…
Part Number: AM3352 Other Parts Discussed in Thread: TFP410 , , AM625 Hi Team,
My customer wants to covert LCD signals from AM3352 to HDMI(no audio needed), could TFP410 implement this function?
Thanks.
Regards,
Charles
Hi Tony,
WP# pin is controlled by bitfield WRITEPROTECT in GPMC_CONFIG like a GPIO.
WP# must be transitioned only when the target is not busy and prior to beginning a command sequence.
The NAND I checked does not support any SW write to enable WP# but…
Part Number: AM3352 Processor SDK5.3, Kernel: Linux localhost 4.14.79-rt47-g28d73230da #38 Tue Jun 7 20:07:18 +14 2022 armv7l GNU/Linux
in customer's system, along large data communication, occasionally file handle can not be used, including socket, UART…
Part Number: AM3352
CPSW in Switch mode.
LLDP protocol needs to support packet from P1 or P2 with destination MAC address 01:80:c2:00:00:0e send to P0 only, not forward between P1 and P2 automatically.
As there was customer implemented it already which…