Now I tried using code given in TI Sysbios for Coretx A8 cache lock (C:\ti\bios_6_76_03_01\packages\ti\sysbios\family\arm\a8\Cache_asm_gnu.sv7A) but same behavior.
Also as I was trying to lock some critical code in cache and my observation is that execution…
Part Number: AM3356 Hi, We are using AM335x in our application and want to use hardware crypto engine. In SDK/PDK i didn't find information for getting started with this feature
Need support for this. Thanks, Mital Pawar
Part Number: AM3356 Hi, My customer wants to use DMA for UART3 transfer. OS is SDK Linux. Q1) Could you tell me how to enable DMA for UART3? Q2) Can UART3 with DMA support up to 1Mbsp? Thanks and regards, Koichiro Tashiro
Hello Eby,
The recommendation is to connect separate VBUS for design flexibility.
Using a common VBUS creates dependency on the operation of the 2 ports.
Regards,
Sreenivasa
Hi, Schuyler
Are there any update about follows?
Takeharu Katsuyama said: But, the frame-order-changing still occurs in both 4.19 and 5.10 kernel. So, my next assingment is this. I found next URL about this. e2e.ti.com/.../4630486
Is this a problem of H/W…
Part Number: AM3356 Hi community,
i am just trying to run the profinet example on a Sitara processor AM3356. When i load the project i am able to build the example but if i try to debug these two error messages are displayed.
Do Someone has an idea what…
Part Number: AM3356 Hi expert
I have a trouble that CPU can't enter to sleep mode in very high temperature environment, because of a H/W problem of POW and CD signals handling for SD card.
I seems, when POW signal becomes high level in very high temperature…
Hi Andy, Thank you for your prompt response. Since this issue is fixed, please create a separate E2E thread to discuss more about the CPM ISR miss. Regards, Laxman
Part Number: AM3356 Other Parts Discussed in Thread: AM3354 We are using the AM3356 processor which performs TCP/UDP communication over the eth0 and eth1 ports.
We are using the CPSW to handle the 2 ethernet ports.
Our implementation on the CPU is an…
Hi,
I do not have any new update here. From previous discussions I see there was some inconsistency in PHY register values between the working and non-working case. For this I had asked to check for the 4 points mentioned in my previous 2 replies. If there…
