Part Number: AM5718
Hello,
Please forgive me if I am asking newbie questions since I am fairly new to an embedded system. I am trying to enable storm prevention from the Linux kernel. I am using dual emac and eth2 and eth3 as my bond0. I have referenced…
Part Number: AM5718 Hi,
We are running into the same issue as this post on an AM5718 board. All software is based on latest PSDK v 06_03_00_106. Looking at kernel source, the dra7xx-clocks.dtsi file has the encoder clock DPLL still set to 388MHz:
From …
Hi,
balaji S said: Iam trying to build the cc66 drivers.
Are you trying to build examples or library?
Also, can you please mention the SDK version you are using?
balaji S said: "../main.c", line 1: fatal error #1965: cannot open source file "ti/board/board…
Part Number: AM5718 I have to read and write from the physical memory (system ram ). I used ioremap to map the region . Device tree setup is also done. Reading works fine.
I use ioread32 for reading and it works fine.
When I used iowrite32 it does does…
Part Number: AM5718 Hi,
Customer encountered a problem when using A15 core and DSP core to read and write CMEM at the same time:
1、There is no problem with CMEM reading and writing data
2、In a CMEM space, A15 changes and writes data in a 1ms cycle each…
Jerome,
yes these MAC IDs are taken from the TI pool. They are unique. you can either use them directly, or use your own pool of MAC IDs.
sorry for the delayed response.
Jian
Part Number: AM5718-HIREL Other Parts Discussed in Thread: AM5718
Hello. I am trying to achieve SPI communication between two AM5718 based custom boards, one of which is master (Linux) and the second is slave (TI-RTOS). The slave is able to receive frames…
Part Number: AM5718 Other Parts Discussed in Thread: DRA722 , PMP
hi,
i have been working in am571xx custom
i enable the USB option but the kernal is not fully loding
if dissable the USB option that time linux kernal of loaded filly and login promt is…
Part Number: AM5718 When using a DDR3 memmory, how do you initiate the HW leveling? The TRM specifically dose not reccomend SW leveling and that one should use HW leveling instead. As seen in the note in 15.3.4.8.2 Software Leveling. There is precious little…
Part Number: AM5718 Looking into the TRM (spruhz7j) for the AM5718 table 15-139, there appears to be a typo in the description of bits 16:12 T_RAS:
"Minimum number of DDR clock cycles from Activate to Precharge, minus one. T_RAS value needs to be…
