Hi Ilia,
Ilia Goland said: Just after first run: DCAN_INT = 8 DCAN_ES = 7
Looks like interrupt status is not getting cleared, which is preventing the new interrupts.
Did you make any changes in DCANAppIsr API of the example. If yes, can you please confirm…
Part Number: AM5726 Hi Guys,
2 questions:
1. Is access to GPMC from c66 cached?
2. Why line Cache.setMarMeta(0x8020000, 16*1024*1024, 0); is not reflected in app_pe66.c
Thanks you very much.
Rasty
Part Number: AM5726 Hi guys,
I need advice.
We would like to transmit data to 4 external devices via SPI.
Need a soft of "fire and forget" mode. Where we write several requests into SPI module, while SPI rises/lowers CS to per requests on its own, without…
Other Parts Discussed in Thread: AM5726 , SYSBIOS Hi,Experts
We are developing AM5726 project at our customer. Current Development Environment:
CCS Version: 9.3.0.00012 on Windows SDK: processor_sdk_rtos_am57xx_6_03_00_106 PDK: pdk_am57xx_1_0_17 OS: bio…
Part Number: AM5726 Hello
I am trying to determine if the AM5726 supports PCIe hot-reset for the following use case of setting up PCIe lanes for an FPGA that is booted from user-space. At the time the kernel initializes the PCIe interfaces, the FPGA is…
Part Number: AM5726
Hello,
I am new on SITARA SoC and I am working on a high throughput system.
I have a question about behavior when several controllers (ARM A15, ARM M4 and DMA) request access at the same time to different devices (McSPI1, McSP2 and…
Part Number: AM5726 Hi experts,
Is it possible to configure a multi-host configuration with multiple cores of AM5726 and connect to two devices (EP) as shown below?
Is it possible with the TI RTOS SDK?
Is there a Library etc. to adopt this method?
Is…
Part Number: AM5726 Other Parts Discussed in Thread: TEST , Hi experts,
My customer wants to do an AM5726 PCIe RX jitter tolerance test. They have been able to perform tests other than PCIe's RX jitter tolerance test without any problems. But they can't…