Hello,
The main feature of LPAE is to allow the mating of larger DDRs with the A15. Another feature-goal is to enable the use of multiple virtual machine for the A15. If your product does not use >2GB of DDR or SW hypervisors with virtual machines then…
Part Number: AM5746 Dear TI Expert
We would like to check the register value of A15 CORE.
By attaching A15 with XDS 100v2, we confirmed that the REGISTER window in CCS enable us to watch PC and other CORE registers like CPSR.
However we would like to check…
Hello Stuart,
Stuart Baker said: In host only mode, the TRM still mentions needing a GPIO for the ID pin (pulled down). Is this still really required, or can the USB interface be configured to be forced into host only mode? It seems rather silly to have…
Part Number: AM5746
Hi Support Team,
I have the following question from my customer who is developing on AM5746ABZXEA.
Please let me know the priority order when Read and Write are done from multiple threads to the same memory address using dual cores…
Hello Tashiro-san, Kobayashi-san,
Q1: Unfortunately this use case is not supported by TI since this use case has not been evaluated on any of our hardware. See this post .
I believe Shreyas is hinting that this is theoretically possible, but it is not a…
Part Number: AM5746 Hello,
Is there some other forum for secure boot related questions?
I saw some other forum post link to secure processor support forum, but the link doesnt work for me. I have access to secure software portal that is provided to my…