Part Number: AM5K2E02 Hello,
We are trying to configure and use a 1000 Base-SX optical SFP with the AM5K2E02 SoC and are having trouble configuring the interface.
We are basing our config code for SerDes, SGMII, MACs and switch initialisation on the…
Part Number: AM5K2E02 with reference to the datasheet Figure 1-2, I can see there is a function called 'Secure Mode'.
However, when I search in the manual or the product page for furher information on what this function does, or how you interact with…
Part Number: AM5K2E02 Other Parts Discussed in Thread: TMDSEMU200-U , , 66AK2E05 Hi Team,
Can you help with the inquiry below?
I am trying to use CCS + Blackhawk XDS200 DEBUG PROBE (TMDSEMU200-U) to load bin files into External NOR Flash (MT25QU02GCBB8E12…
Part Number: AM5K2E02 Tool/software: Hi,
We are using the Short Descriptor format in the ARM MMU; specifically we are using 1MB sections in the First-level table only. This means the section entries in our Level-1 table are defined bits [31:20] of our…
Part Number: AM5K2E02 Hi,
Due to some internal processes, I need to answer some legal/regulatory questions regarding third party software used in our product.
As the ARM ROM Bootloader (RBL) constitutes software (or firmware), this falls under this…
Part Number: AM5K2E02 Hi,
Are you able to confirm the input leakage current for the DDR3VREFSSTL DDR3 reference voltage pin. Input current is stated for I2C and LVCMOS(1.8V) pins under Electrical Characteristics but it is unclear if the DDR3VREFSSTL…
Part Number: AM5K2E02 I am looking for if you have the A 0 (Scaling Factor have as per the failure mechanism equations as per the example below for calculating the TTF value.
The Scaling factor will be for each failure mechanism i.e. Electromigration…
Part Number: AM5K2E02
Hi all
In Table 6-22 of SPRS864D, we have system events 30 (PCIE_0_INT4) and 32 (PCIE_0_INT6). But both of these are described as "PCIE MSI Interrupt". How do I choose which one to use? What's the difference?
Likewise Table…
Part Number: AM5K2E02 Hi Experts,
I am working on a DDR3 driver, using the TI document SPRUHN7C (Keystone II DDR3 Memory Controller). The target hardware is AM5K2E02 (Keystone II SoC).
In section 4.58 (Impedance Control Register 1) there is a ZQnCR1…