Part Number: AM6442 Hi Team, We are planning on development of custom board design, in AM6442 HLD we could able to see two ICSS PRUs available in AM6442,so my question is can we able to design two seperate ethercat in/out ports using two ICSS(ICSS0 and…
Part Number: AM6442 Hello,
I’m looking for information about the MSRAM:
What is the bus width?
What is the access latency from the A53 and R5F cores?
I’m designing a simple, low-latency protocol to transfer only a few tens of bytes. The R5F…
Part Number: AM6442 Other Parts Discussed in Thread: SYSCONFIG Dear TI Team, I encountered issues while testing the overhead from triggering a timer interrupt to entering it, and I would like to seek your advice. First, in an empty project, I configured…
Part Number: AM6442 Hello TI Team,
We are performing thermal simulations of the AM6442. However, we have not been able to find any information on the thermal power dissipation .
We are using the sprm779_Power Estimator Excel file to estimate the power…
Part Number: AM6442 Does the J-Link debugger support debugging for both the Cortex-R5 and Cortex-M4 cores on the AM6442 processor? Please confirm the compatibility.
Part Number: AM6442 Tool/software: I’m evaluating the AM6442 (AM64x family) for a project that requires strict compliance with certain TSN standards. I have reviewed the datasheet, SDK release notes (SPRT769), and driver documentation, but I could not…
Part Number: AM6442 Hi Team, I could see in AM6442 datasheet that two dual remote cores available(totally 4 R5F cores) so I just want to enable remotecore R5F1_0 in AM6442 processor, By configuring r5f in defconfig of TI RT Linux version 9, remoteproc0…
Part Number: AM6442 Hi Team,
I was going through the following thread " AM6422: cpsw ICSSG - Processors forum - Processors - TI E2E support forums ".
In our custom AM6642 board we have implemented 5x Ethernet (1x CPSW, 2x ICSSG0, 2x ICSSG1) . ICSSG…
