Part Number: AM6526 From Table 6-1 in the AM65xx datasheet (Pin Attributes) we see most pins are "HI-Z" at RESET.
I am supporting an application where the GPMC address pins (GPMC0_A**) are connected to MRAM; they are not PU/PD externally.
We are internally reviewing based on the available information.
I still do not have an update to share.
I assume this is not stopping any of the development on your side.
Sorry for the delay. We don't have a table in the same format. If this is to determine power supply capacity, TI recommends that you refer to the AM65x IDK implementation and either follow that exactly or choose components that are equal…
In general yes the TRM and specifically the memory map has gone through the release process and reviews, but clearly at least this error got through. The MSMC3 related memory map section does not contain other errors, the way this got through did not…
Part Number: AM6526 Hello,
I am considering to adopt this processor, or a similar one belonging to the same family for an application with a lot of connectivity requirements.
I would like to use android as OS, but since I have never done this before I…
For others that might be concerned, the overall end to this thread is summarised as:
1) USBSS "LPM" mode capability is an unsupported feature
2) The register that affects LPM entry acceptance/initialization is PORTPMSC2. In TI…
Part Number: AM6526 This question deals with the following Literature: https://www.ti.com/lit/an/spraar7i/spraar7i.pdf
“Maintain constant trace width after the SoC BGA escape to avoid impedance mismatches in the transmission lines.”…