There does not appear to be any further granularity to inside any ERR_SYS error being set, and thus best to treat as fatal error. Refer to the PCI Express Base Specification on how to handle ERR_FATAL, ERR_NONFATAL and ERR_CORR.
Part Number: AM6548 Tool/software: From https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1350912/mspm0l1305-to-add-arm-compiler-for-embedded-v6-19-compiler-in-ccs…
Part Number: AM6548 Tool/software: Hi Ti,
We are using AM6548 with Linux RT SDK now and we have our program running inside PRU.
Below is our IEP setting and we use CT_IEP0 for PRU0_0 and PRU2_1.
void IEPTimer_init(void) { /* Set PRU Sync-to-VCLK Mode…
Part Number: AM6548 Tool/software: Hi, support team!
We are building an RTOS system using only two cores in one cluster of AM6548.
Recently, we expanded this system to use two clusters (four cores), but it seems that cache coherency cannot be maintained…
Part Number: AM6548
Tool/software:
Hi Ti,
We are using AM654 with Linux RT SDK 7 and we have 2 usb ports. usb0 as peripheral and usb1 as host mode. Both mode works well.
usb20_host_pins_default: usb20_host_pins_default { pinctrl-single,pins = < AM65X_IOPAD…
Part Number: AM6548 Tool/software: Does the MCU_MSRAM have ECC enabled by default? We believe that the ECC is always active, but not sure how to verify. We're exercising the R5F core while the A53 is in idle loop.
Sorry for late reply.
Test program we use has problem. And, we fix it, then test program works well.
At the moment, the test program is functioning as expected on all four cores.
Thanks for your support !
Hello Andrea,
It looks like there IS interrupt connectivity between all GPIO modules and the R5F cores. I will not be able to guide you on setting up that interrupt routing, however.
How to see interrupt connectivity
I checked this part of the TRM for…
Ronald Wahl said: the R5F came to halt.
Thanks for this confirmation. I've positioned the associated ticket (SITSW-6185) accordingly internally. It would seem that most of the public DM FW would be affected (https://git.ti.com/cgit/processor-firmware…