Hi Jerry,
Are you referring to the parallel LVDS data or the serialized SDI data?
The parallel LVDS data is in an FPGA DDR format, and there is example code available for the FPGAs: http://www.ti.com/tool/broadcast_video_serdes_ip . For more details about…
Hi Lian,
Yes LMH0340 and LMH0341 can support 1080p30 or 1080p25. However, please note these devices have 5 LVDS signal pairs plus clock pair and require external FPGA. FPGA IP provides 5 LVDS pairs to 20 bits interface (like LMH0030/LMH0031). Please below…
Hello,
Please take a look at LMH0340/LMH0341 FPGA IP. Here is a link to this solution and documentation:
http://www.ti.com/tool/broadcast_video_serdes_ip
Please note: This IP supports 3G SDI video frame formats(on top of HD and SD video frames).
Regards…
Greetings Satoshi-San,
LMH0340/LMH0040 uses FPGA to generate different video frame format. I believe the present FPGA IP supports items 1,3, and 4. I am not sure about YCbCr 4:4:4. Customers use present FPGA IP and add additional features like 4:4:4 support…
Hi Sam,
We provide FPGA IP to convert video from SDI to SMPTE Bt601 10 or 20 bits format. Here is a link to this FPGA IP:
www.ti.com/.../broadcast_video_serdes_ip
Then you would need additional FPGA IP to communicate and convert this video to FPD-Link…
Hi Roger,
FPGA IP converts 5 LVDS pairs of LMH0341 to 20 bits to decode SDI framing to generate SAV and EAV, and other SDI frame related items. In summary, LMH0341 does not decode SAV anbd EAV and these are done by the FPGA IP. Please below note a link…
Other Parts Discussed in Thread: LMH0340 , LMH0341 Hi,
I would like to ask you a question about FPGA IP for DVB-ASI interface by using LMH0340/0341.
This question is from my customer.
There seems to be some FPGA IPs for DVB-ASI on the following web page…
Ramin
I would suggest staying with the LMH0071, and working around the DVB-ASI issues with IP in the FPGA. There is some enhanced DVB-ASI support code here: http://www.ti.com/tool/broadcast_video_serdes_ip
Mark Sauerwald
