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Showing 20 results View by: Thread Post Sort by
  • CD74HC4094: flow soldering(DIP)

    Yasushi Fujiwara
    Yasushi Fujiwara
    TI Thinks Resolved
    Part Number: CD74HC4094 Hello Experts, My customer asked me whether CD74HC4094PWR can be flow soldering(DIP) or not. Would you please answer it? Best Regards, Fujiwara
    • over 4 years ago
    • Logic
    • Logic forum
  • CD74HC4094: CD74HC4094

    Hollis Liu
    Hollis Liu
    Part Number: CD74HC4094 Hello, Customer has issue of CD74HC4094 in serial to parallel application. Customer use CD74HC4094 to extend the IO of MCU. And they found sometimes the output has no update when the input data and clock is normal. The power…
    • over 8 years ago
    • Logic
    • Logic forum
  • CD74HC4094: Data transition of QS2

    Nam, Dino
    Nam, Dino
    Part Number: CD74HC4094 Dear team, At datasheet of CD74HC4094, we can see QS2 data transition(white box1) when CP is negative edge. but please refer to the below waveform. My customer why QS2 data is changed low to high when CP is positive edge(white…
    • over 6 years ago
    • Logic
    • Logic forum
  • CD74HC4094: Does this have reset?

    Jeff Hawkins69
    Jeff Hawkins69
    TI Thinks Resolved
    Part Number: CD74HC4094 Our system specifically requires that upon system bootup, all outputs be low. Will a system shutdown/loss of power reset this device? We cannot rely on proper shut procedure for this application. The enable line is currently pulled…
    • over 7 years ago
    • Logic
    • Logic forum
  • Answered
  • CD74HC4094: Function table

    user4109590
    user4109590
    Resolved
    Part Number: CD74HC4094 Hello E2E Logic Forum Members, Our customer asked us the function which is not described in the datasheet. Would you please input the function to ??? in the below table? INPUTS PARA OUT SER OUT --------------------…
    • Resolved
    • over 7 years ago
    • Logic
    • Logic forum
  • RE: SN74LVC1G34DRL Power Up Logic 1 Behaviour

    ShreyasRao
    ShreyasRao
    Hi Jose , I assume you are talking about SN74LVC1G74 . I have attached an app note on the behavior of clocked devices . The output at startup is not guaranteed until a valid clock input signal comes in . 5277.powerup_clockeddevices_scha005a.pdf
    • over 10 years ago
    • Logic
    • Logic forum
  • RE: CD4541B - Power up state of Q output and Autoreset with 5V supply

    ShreyasRao
    ShreyasRao
    Hi Kiran , I have attached an app note explaining the initial state on power up for the clocked devices . During power up , the Q and Q/ would be complimentary but not determinate . Once the power up is done and with valid clock or input , the outputs…
    • over 10 years ago
    • Logic
    • Logic forum
  • Answered
  • RE: As the flip flop 's the CD4013 chip , go to the initial state Q 0 and Q BAR 1 , when the circuit is energized ?

    ShreyasRao
    ShreyasRao
    Resolved
    Hi Tarcisio , You are right about the initial state for the CMOS circuits . they are undefined until a valid signal is applied .In case of clocked circuits ,the output is indeterminate before valid clock signal comes in . I will attach an app note explaining…
    • over 10 years ago
    • Logic
    • Logic forum
  • RE: 74HCT

    ShreyasRao
    ShreyasRao
    This device has a master reset which when activated (low) will keep outputs at logic low regardless of the clock or data input .You can tie this to Vcc through pullup resistor which should have the outputs low . The behavior of clocked devices output…
    • over 10 years ago
    • Logic
    • Logic forum
  • Answered
  • RE: Driving of two pin dual color LEDs using TLC59116 driver

    Adam  Hoover
    Adam Hoover
    Resolved
    Hi Mahabir, Thanks for sharing your schematic! Please confirm I correctly understand: You are sourcing the LED current directly from the output of the 74HC595. When a particular 74HC595 output is on, this powers an entire row of LEDs. The TLC59116…
    • over 11 years ago
    • Power management
    • Power management forum
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