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Showing 22 results View by: Thread Post Sort by
  • DP83826AI: DP83826AI MDIO questions

    Sean Liao (Yu-Sheng)
    Sean Liao (Yu-Sheng)
    TI Thinks Resolved
    Part Number: DP83826AI Hi sir, DP83826AI MDIO pin fuctions is mentioned there's internal 10kohm pullup resister in datasheet But in datasheet, it still mentioned that need a pullup resisitor, and the design checklist also says the external pull…
    • 7 days ago
    • Interface
    • Interface forum
  • DP83826AI: Issue with EtherCAT slave using DP83826A

    AhmadBashar Taji
    AhmadBashar Taji
    Part Number: DP83826AI I have developed a code for XMC4800 evaluation board which uses BCM5241XA1KMLG and it is working fine. Since it became absolute, I switched to DP83826A, and used the same working code, and added some additional code to configure…
    • 1 day ago
    • Interface
    • Interface forum
  • Answered
  • DP83826AI: better EMC performance: Strap11 High.

    Roberto Bottini
    Roberto Bottini
    Resolved
    Part Number: DP83826AI Dear all, I read in the ‘Difference Between DP83826x and DP83826Ax’ document that, for best performance, TI recommends enabling only the Signal/Energy loss FLD mechanism or disabling FLD. Immediately afterwards, it adds: ‘To…
    • Resolved
    • 2 months ago
    • Interface
    • Interface forum
  • DP83826AI: Can DP83826AI be used instead of Renesas, UPD60610?

    Kazuya Nakai59
    Kazuya Nakai59
    TI Thinks Resolved
    Part Number: DP83826AI Tool/software: Hello guys, One of my customers is looking for a Ether-PHY which can replace Renesas, uPD60610 with. uPD60610(Single Channel 10/100 Ethernet PHY) https://www.renesas.com/en/document/fly/pd60610?srsltid=AfmBOorUI0y6uWoHLPxI4O4eCCX1inu…
    • over 1 year ago
    • Interface
    • Interface forum
  • Answered
  • DP83826AI: PHY address

    利幸 酒井
    利幸 酒井
    Resolved
    Part Number: DP83826AI According to “Table 8-44. PHYCR Register Field Descriptions” in the DP83826AI datasheet, the PHY address is 5 bits. However, I can only find three strap pins for the PHY address. Which information is correct? If the PHY address…
    • Resolved
    • 4 months ago
    • Interface
    • Interface forum
  • Answered
  • DP83826AI: 10BASE T

    利幸 酒井
    利幸 酒井
    Resolved
    Part Number: DP83826AI Other Parts Discussed in Thread: DP83822I Does the DP83826AI support 10BASE-T, or is it limited to 10BASE-Te only? Based on the description in the datasheet, I understand that EEE is disabled by default. In this case, is it correct…
    • Resolved
    • 4 months ago
    • Interface
    • Interface forum
  • DP83826AI: Mismatched setting of Auto-MDIX between strap and register value

    AhmadBashar Taji
    AhmadBashar Taji
    TI Thinks Resolved
    Part Number: DP83826AI Hello, The DP83826A is designed to provide EtherCAT connectivity. For that, it was designed to operate in enhanced mode (ModeSelect = floating), and the strap9 is set to 0 and it was confirmed using register SOR1. This should…
    • 3 days ago
    • Interface
    • Interface forum
  • DP83826AI: Impedance control for DP83826A signal

    Ryuuichi machida
    Ryuuichi machida
    TI Thinks Resolved
    Part Number: DP83826AI Hi, Let me confirm meaning of following sentence which is described datasheet of DP83826A. 9.4.1.1 Signal Traces * Unless mentioned otherwise, all signal traces must be 50ohm single-ended impedance. In general, impedance control…
    • 4 months ago
    • Interface
    • Interface forum
  • DP83826AI: Questions of LED0/Strap2 pin and CEXT pin.

    Motoyasu Hattori
    Motoyasu Hattori
    Part Number: DP83826AI Hi, We have two questions of DP83826AI. On LED0/Strap2 pins, Default value is different between Enhanced mode and Basic mode. Depend on mode, Internal Pull-up/down resister is changed. Is it correct? According to the datasheet…
    • 1 month ago
    • Interface
    • Interface forum
  • DP83826AI: Packet alignment and preamble length

    Dom
    Dom
    TI Thinks Resolved
    Part Number: DP83826AI Dear support team, the microcontroller we're planning to use has an Ethernet MAC with specific requirements regarding the packet alingment and preamble length, limiting the number of interoperable PHYs. In 10 MBit mode the MAC…
    • 7 months ago
    • Interface
    • Interface forum
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