Other Parts Discussed in Thread: DP83865 Hi,
I was wondering if this phy supports 100Mbps RGMII. There is no timing diagram for this mode on page 77 of the data sheet and Table 42 does not indicate that it's a valid controller i/f for 100Base-TX. The confusing…
Other Parts Discussed in Thread: DP83865 Hi,
I'd like ask about DP83865(Giga Ether Phy) as follows,
In DP83865 D/S page66 5.7 Twisted Pair Interface, There is some description about the twisted pair impedance as follows,
"50-Ohm controlled impedance…
Other Parts Discussed in Thread: DP83865 Hi,
I am facing the following issue in using dp83865. Please see below the problem description.
I am following the following sequence to initialize the phy dp83865
Master Clock is given to the PHY, at pin number…
I am trying to get the transmitter BIST to work but the phy does not seem to be transmitting anything as observed in the network card status window that shows how many packets was sent and received.
The cable is directly between the phy and the pc.
The…
Other Parts Discussed in Thread: DP83865 In our customer's boards, the 1.8V supplies (i.e. CORE_VDD and 1V8_AVDDx) are powered up at the same time prior to the other supplies (i.e. IO_VDD and 2V5_AVDDx). Until the other supplies are powered up, the other…
Other Parts Discussed in Thread: DP83865 Hello.
Please teach it about pin connection when Customer uses only 100BASE in Ether phy DP83865/DP83867 for 100/100BASE.
Customer will not use C port and D port P/N pair of the Ether side,
When you are not connected…
Hi,
The MAC will be communicating to the phy in the following way:
1) RGMII for both 100Mbps and 1000Mbps.
2) We will be streaming data as fast as the link allows so the internal status registers of the PHY will be accessed very rarely. Probably after…
Other Parts Discussed in Thread: DP83865 Hi,
I have been having an issue with transmitting data using the DP83865 PHY. I am running in 100 Mbps mode and have been able to receive data into a FPGA. Since the data comes in with the LSB first, I swap nibbles…