Part Number: DP83867CS Hi Team,
We are using DP83867CS PHY for our SGMII Interface 10/100Mbps
We are getting MDI Link up.
But we couldn't able to ping the device.
Please find the register dump below.
=> mdio read FM1@DTSEC9 0-0x1f Reading from…
Part Number: DP83867CS Tool/software: Hi TI team.
I have a custom board with ZYNQ ultrascale +.
It is connected to two DP83867CS by an SGMII PS port.
I am working with petalinux OS.
on the eth1 port, everything is OK,it obtains IP automatically.
However…
Hi Alvaro,
Thank you for answering.
We are evaluating whether we can switch from DP83867CS to DP83869HM.
It may spend some time. When I have additional questions, I may ask you again.
Best Regards,
Part Number: DP83867CS Dear support team,
we determined a functional failure after reset. It is assumed that the RESET_N input of the IC with a newer batch of DP83867CS casing the problem. The reset signal is connected to a capacitor to make it more robust…
Hi User,
I am not sure how many mV will increase per value of A0. I do not have the bandwidth today to go into lab and check today but please feel free to adjust this register and see the effects it has on the waveform.
Regards,
Alvaro
Part Number: DP83867CS Hi,
The following threads state that registers may need to be set depending on the value of the clock offset.
https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1198616/dp83867cs-jumbo-frame-support/4520299
…
Hi Hillman Lin,
You are right, both cases are linked together. In both cases the same module is used, with same drivers and firmware, but the link partners are different and we have a different error behaviour. And therefore I would propose to handle both…
Hello,Gerome
thank you for answering.
>To adjust VoD, we have Reg 0xA0 and 0xA1. Please note these are trim values. >A0[3:0] adjusts Channel A, while [11:8] adjusts Channel B. >A1[3:0] adjusts Channel C, while [11:8] adjusts Channel D. We were…
