Part Number: DP83869HM Other Parts Discussed in Thread: DP83869EVM , TPS735 Hello,
we want to use DP83869HM for our design. In the datasheet, a minimal ramp-up time of 0.5ms is listed applicable to all power rails. However, if we look at the schematic…
Part Number: DP83869HM Other Parts Discussed in Thread: DP83869 We're using the DP83869HM in bridge mode (RGMII to SGMII).
Datasheet page 95(dp83869hm.pdf) describes the two-supply configuration option. On page 96, it states to strap the SUPPLYMODE_SEL…
Hillman Lin said: For the next steps for debug, are you able to do a MII loopback on PHY2 and check the package on the MAC side to see any package drop? The detail information will be on 9.3.4 in the datasheet or register 0x0000
I now checked what information…
Part Number: DP83869HM Hello,
My customer wants to use the DP83869HM in SGMII to RGMII bridge mode.
To configure SGMII to RGMII brighe mode, the customer connected 4 pins according to following table 9 guide. However, SGMII to RGMII bridge mode setting…
Thanks for your information on queries.
I have one more query on SMI Interface (Serial Management Interface).
As per IEEE 802.3-2022 Clause 22 Section 22.3.4, Delay between MDC and MDIO can be 0ns (Min) to 300ns (Max).
But in DP83869HM…
Gerome Cacho said: so long as there is no swapping who talks with who
Gerome commented: " 2x DP83869's may help with this application so long as there is no swapping who talks with who."
What does Gerome mean when stating: so long as there…
Is there a way to figure out what state the FPGA pins are in after they are programmed ?
Another thing I can think of is that the RX_D0 and RX_D1 pins connected to FPGA might have changed the PHY address state when FPGA is getting programmed…
Part Number: DP83869HM Hi team,
Could you please let me know the unused pin termination for each case below?: 1. RGMII to Copper mode （Serdes-I/F） 2. RGMII to 100Base-X mode (Copper-I/F) 3. Media Converter mode (RGMII-I/F)