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  • DRA76P: PCIe controller and clock configuration in DRA76P

    Mariano Caballero
    Mariano Caballero
    Part Number: DRA76P Tool/software: Hello TI team, My team is developing a custom board with host processor DRA76P, running with Android 8 (Oreo) and Linux kernel 4.4. Currently, we are working in the integration of a JodyW377 BT/WIFI into the SOC. The…
    • 2 months ago
    • Processors
    • Processors forum
  • RE: DRA76P: USB Eye diagram failure

    ShreyasRao
    ShreyasRao
    Augusto, Here is the snippet of the USB drive eye mask improvement.. " The fundamental idea would be to reduce termination resistance by a few counts to improve the eye diagram height. We would recommend tuning termination resistance first and then…
    • 1 month ago
    • Processors
    • Processors forum
  • RE: DRA76P: Power consumption

    kcastille
    kcastille
    Hi Augusto, You can find the DRA76P EVM design files here: https://www.ti.com/tool/J6PEVM577P Including the schematic PDF: https://www.ti.com/lit/df/sprr314/sprr314.pdf Appnote is here: LP87565C-Q1 and TPS65917-Q1 User’s Guide to Power DRA7xxP and TDA2Pxx…
    • 2 months ago
    • Processors
    • Processors forum
  • Answered
  • RE: DRA76P: Connecting i2s (mcasp) to PCM interface (bluetooth)

    Miguel Garcia3
    Miguel Garcia3
    Resolved
    Hi Kile, All is working fine. I don't know but the flag XERR is set in all working interfaces. Regards, Miguel
    • 9 months ago
    • Processors
    • Processors forum
  • DRA76P: When using 2GB of DDR3 it is better to have 4 chips in 1 EMIF or 2 chips in EMIF 1 and 2 chips in EMIF 2

    Leonardo Lomastro
    Leonardo Lomastro
    Part Number: DRA76P Tool/software: I am starting a project with the Micro DRA 767. The idea is to use 2G of DDR3 RAM. Looking at the EVM we can use 4 banks of 8 bits in EMIF 1 or 2 banks of 16 bits in EMIF 1 and another 2 banks of 16 bits in EMIF 2. …
    • 10 months ago
    • Processors
    • Processors forum
  • DRA76P: DRA767PSGACDQ1

    Nigel Taylor
    Nigel Taylor
    Part Number: DRA76P Is a external calibration resistor required for DDR on DRA76xP or is this managed internally if so how?
    • over 1 year ago
    • Processors
    • Processors forum
  • DRA76P: Disable CAN bus from vision_sdk rvc

    Miguel Garcia3
    Miguel Garcia3
    Part Number: DRA76P Hi, We are using SDK v6AO.1.1, android 8.1, linux kernel 4.4.117, and vision_sdk to manage cameras. When we are displaying cameras images from IPU2 and using CAN from Android (linux 4.4) after some time, we get: [ 702.034663] omap_hwmod…
    • over 1 year ago
    • Processors
    • Processors forum
  • Answered
  • DRA76P: Image issues with ti,vip1 connected to adv7611 (HDMI input)

    Miguel Garcia3
    Miguel Garcia3
    Resolved
    Part Number: DRA76P Hello, We have an issue capturing images with the vip1 and adv7611 in linux. We think the chip is correctly configured for 1920x1080 30Hz but the captured images are not fine, they are cropped, flattered and the color is not ok. A…
    • Resolved
    • over 2 years ago
    • Processors
    • Processors forum
  • DRA76P: How to configure McASP to receive PDM?

    Marek Wardzinski
    Marek Wardzinski
    Part Number: DRA76P Hello. My client have hardware solution with 2 MEMS MIC with PDM (MP34DT05-A) connected directly to McASP6 (aclkx, axr0). In the other topic your answer was "PDM audio can be captured with McASP.". Is it possible, and how to configure…
    • over 2 years ago
    • Processors
    • Processors forum
  • Answered
  • DRA76P: can ti RTOS support cache flush for a certain address for tda2/dra76x

    Semon Zhang
    Semon Zhang
    Resolved
    Part Number: DRA76P Other Parts Discussed in Thread: TDA2 customer have video processing issues on DRA762/TDA2, when use VPE to process video data, vide data in buffer will be cached, after using hardware accelerate feature,parts of data in the cache is…
    • Resolved
    • over 3 years ago
    • Processors
    • Processors forum
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