Part Number: DRA77P Tool/software: Hi all,
I need to know if DRA77P if one of its IPU is capable of managing Ethernet the same way it can take control of a DCAN / MCAN. I think the exact question is : Can the IPU access GMAC_SW0 or GMAC_SW1 interfaces…
Part Number: DRA77P Tool/software:
Hello.
I would like to know if you have more information on PI Modelling and Validation or PDN Design Guides that, for example, include more practical examples such as those in point 7.3.8 of the Processor Datasheet…
Part Number: DRA77P Hi
As the original question is closed without any comments, I ask the same question again:
We're having issues with this setup: - DRA77P EVM board, - USB3.0 A to microB cable - PC with USB3.0 connectors - mini-USB to USB connector…
Part Number: DRA77P Hi team,
Here's an issue from the customer may need your help:
Is there a hardware JPEG encoding module for the DRA77P? If so, how much throughput does it have? If not, is there an alternative? The throughput required is 720p,…
Hello, Thank you for your question. Unfortunately, this device does not support hardware JPEG functionality.
The SDK document below is for DRA77xP device which can be accessed from below links have the multimedia capabilities.
https://www.ti.com/product…
Part Number: DRA77P Hi We're having issues with this setup: - DRA77P EVM board, - USB3.0 A to microB cable - PC with USB3.0 connectors - mini-USB to USB connector. When we stop u-boot and enter fastboot 0, the USB3.0 is reconiced by Windows but with problems…
Part Number: DRA77P Hi everybody ,
I m doing SW leveling and woudl like to be sure at boot time everything done properly
is there any register or SW way to cross chek everything run adn done properly as exepcted ?
thank you
BR
Carlo
Part Number: DRA77P Hi,
We've designed a new PCB based on DRA77P with 4GB, so we're using two EMIF. With one of the EMIF we've done what is desceribed on Figure 7-55. 32-Bit, One-Bank DDR3 Interface Schematic Using Two 16-Bit DDR3 Devices…
Part Number: DRA77P We are finding some devices of DRA777PSIGACDRQ1 that not work properly at audio I/O data stream(with I/O delay configuration), if we not put I/O delay configuration, the device can work properly. What is the reason for this abnormity…
Part Number: DRA77P Hi,
I have read the erratasheet (SPRZ450A) and I have some questions regarding the item "i862. Reset should use Porz". I have assembled a PCB with the PMIC of the EVM, the O917A154TRGZTQ1, so I have gone directly to implementation…
