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  • DRA821U: Follow-up Regarding GPIO Toggle Verification on DRA821U

    Part Number: DRA821U Hi Team, I had previously posted a query regarding GPIO toggling in the below forum thread. However, due to a technical issue, I am unable to reply in the same discussion thread: https://e2e.ti.com/support/processors-group/processors…
    • Answered

  • DRA821U: DRA821U: Timeout during frequency handshake

    Resolved
    Part Number: DRA821U Hi, We have a new revision (B) of our custom board based on the DRA821U. Previously, we posted about the bring-up of revision A HERE . At the moment, we are uploading the boot stage through MCU_UART. Specifically, we are loading…
    • Resolved

  • DRA821U-Q1: DRA821U-Q1 LPDDR4 configure optimization

    Part Number: DRA821U-Q1 Other Parts Discussed in Thread: DRA821 , SYSCONFIG Issues: DUT stops booting in rare cases, it may say kernel panic, or other message, see ticket: https://e2e.ti.com/support/processors-group/processors/f/processors-forum…

  • DRA821U: Support Required for 10G Interface Configuration on DRA821U

    Part Number: DRA821U Other Parts Discussed in Thread: SYSCONFIG , DRA821 Hi Team, We are currently working on validating the 10G interface on the DRA821U processor. We had previously raised a support query (link below) and followed the same configuration…
    • Answered

  • DRA821U: Support Required: MCU SPI1 Issues with SRAM and TPM on DRA821U

    Resolved
    Part Number: DRA821U Other Parts Discussed in Thread: DRA821 , SYSCONFIG , TPS6594-Q1 Dear Team, We have connected SRAM ( 23A512-I/SN ) and TPM ( ATTPM20P-H6MA1-10 ) to the MCU SPI1 interface as slave devices on the DRA821U platform and added the corresponding…
    • Resolved

  • DRA821U: DRA821U MCSPI Transactions

    TI Thinks Resolved
    Part Number: DRA821U Other Parts Discussed in Thread: SYSCONFIG We are using the DRA821U MCSPI interface to communicate with FPGAs on our board. Each SPI transaction is a 64-cycle frame where chip select is continuously active. Each transaction is always…
    • Answered

  • DRA821U: DRA821U: Can not transmit/receive frames with ETHFW

    Resolved
    Part Number: DRA821U Hi, this question is related to the thread "DRA821U: Can not receive frames with ETHFW" https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1587865/dra821u-can-not-receive-frames-with-ethfw Unfortunately…
    • Resolved

  • DRA821U: DRA821U: SRAM write issue

    Part Number: DRA821U Other Parts Discussed in Thread: TMP421 Dear Team, We are using DRA821U processor in our project. We have connected the 23A512-I/SN SRAM to the DRA821U over SPI. In the device tree (dts) we have configured the spi-max-frequency as…

  • DRA821U: Guidance Required for Implementing 10G Interface on DRA821U

    Part Number: DRA821U Other Parts Discussed in Thread: DRA821 Hi Team, We are planning to implement the 10G interface on the DRA821U processor. Could you please guide us the implementation required to support and validate the 10G interface on DRA821U?…

  • RE: DRA821U: DRA821U: Serdes output clock to support PCIe

    Unlocking and linking new thread: RE: DRA821U: Update on lowpower mode and pcie clock Regards, Takuma

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