Part Number: DRA821U Dear supporter,
In my n ewly developed device like the PROC105E8(001) have multiple power supplies from the PMIC(TPS65941515RWERQ1) to DRA821U4/LPDDR4.
Is the resistance of the power supply line a few ohms normal? 0.8V: VDD_CORE line…
Part Number: DRA821U Other Parts Discussed in Thread: SYSCONFIG , DRA821 Hi TI
A customer would like to know if the current version of SysConfig tool would be able to support SR2.0 as well even though the tools does not contain SR2.0 item in the device…
Part Number: DRA821U
Customer would like to know the difference btw RTM version and below.
Can you please let us know if there're major changes from RTM version?
They would like to know what the following materials are different from the RTM version…
Part Number: DRA821U Hi All,
I can find the power estimation toll for AM64x and AM62x from TI website.
Does TI provide the similar tool to calculation the power consumption for DRA821U based on different utilization at different junction temperature? …
Part Number: DRA821U
Dear TI Team,
We saw an issue with ALE aging timer. Currently, our ALE timer is set to ~38sec.
The ALE table is initially configured as “Not learned with the source address” (CPSW_ALE_CONTROL 0C03 E008h, bit 7 is set) …
Part Number: DRA821U Other Parts Discussed in Thread: DRA821 Champs,
I see some signs that work has been done to enable cpsw5g in uboot: https://email@example.com/ .
Is this going to be available…
Part Number: DRA821U Other Parts Discussed in Thread: DRA821 Hi,
We are developing a new product called Automotion Server that is one is a evolution on a existing product.
The new product will be based on DRA821 processor.
The existing product is using…
Part Number: DRA821U As shown below, TRM (page 4980) describes the timing of FIFO underflow interrupt generation.
"If you read when FIFO is empty, it will trigger an underflow interrupt."
However, when we tried on EVM, the FIFO underflow interrupt…
Part Number: DRA821U Hi TI Team,
We are looking for procedure to set ALE_AGING_TIMER to 10sec.
By default, we read value of this register as 0x141(321 dec).
Thinking number of clock cycles might be for R5F processor (1GHz). Our understanding is default…