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Showing 289 results View by: Thread Post Sort by
  • DRA829J: Set module clock parent via direct registers access

    Antonio Pinto
    Antonio Pinto
    TI Thinks Resolved
    Part Number: DRA829J Tool/software: Dear TI-Team, Clocks with the name _PARENT_ are not directly fed to the module but feed into a multiplexer and then based on the value of the multiplexer will reach the module. See FAQ: https://software-dl.ti.com…
    • 1 month ago
    • Processors
    • Processors forum
  • Answered
  • DRA829J: Porting CAN application to a different core in DRA829J

    Eduardo Beltran
    Eduardo Beltran
    Resolved
    Part Number: DRA829J Tool/software: Hi TI, I´ve been compiling/setting up a can_app example for DRA829J MCU 3_0 . Originally in PSDK there is support only for cores 1_0 and 2_1 , and I found that If I want build can_app for core 3_0 I need to follow some…
    • Resolved
    • over 1 year ago
    • Processors
    • Processors forum
  • DRA829J: Procedure to change clock source

    Antonio Pinto
    Antonio Pinto
    Part Number: DRA829J Tool/software: Dear Ti Team, We are changing the clock source to many modules through the CLK_SEL field in the corresponding register. However we would like to clarify if besides setting CLK_SEL bits to change clock source, an additional…
    • 4 months ago
    • Processors
    • Processors forum
  • Answered
  • DRA829J: CPSW9G behaving like a hub

    Matthias Hörger
    Matthias Hörger
    Resolved
    Part Number: DRA829J Other Parts Discussed in Thread: TDA4VH-Q1 , TDA4VH Tool/software: Hi, We run CPSW9G in native ethernet configuration with SDK 11. Two (or more) external switch ports belong to the same VLAN. On A72 we also use this VLAN to receive…
    • Resolved
    • 1 month ago
    • Processors
    • Processors forum
  • Answered
  • DRA829J: CPSW9G VLAN priority not working

    Matthias Hörger
    Matthias Hörger
    Resolved
    Part Number: DRA829J Tool/software: Hi, We run CPSW9G in native ethernet configuration with SDK 11. On sending, VLAN packets with priority 6 are not sent on the ports tx_pri6 queue. All packets are send via tx_pri0. On receiving, VLAN packets…
    • Resolved
    • 4 months ago
    • Processors
    • Processors forum
  • Answered
  • DRA829J: CPSW9G interrupt overview

    Matthias Hörger
    Matthias Hörger
    Resolved
    Part Number: DRA829J Tool/software: Hi, I'm trying to better understand the interrupt handling of CPSW9G. We run CPSW9G in native ethernet configuration. On egress from the CPU, the RX counter of host port p0 is increas ed (p0_net_octets). Sinc…
    • Resolved
    • 6 months ago
    • Processors
    • Processors forum
  • DRA829J: Power Estimation Tool

    Ben Alford
    Ben Alford
    Part Number: DRA829J Tool/software: I am starting a hardware design using the DRA829J and would like access to the Power Estimation Tool. Besides the power estimation tool are there any other guidelines? I am interested in several related aspects…
    • 7 months ago
    • Processors
    • Processors forum
  • DRA829J: DRA829J

    Philipp Thiel
    Philipp Thiel
    Part Number: DRA829J Other Parts Discussed in Thread: DRA829 , TDA4VM Dear Team, I want to ask if there's a new file or solution loading J721E_DRA829_TDA4VM.bsm file in Goepel BoundaryScan Software. If I try to load it, there are many logical errors…
    • over 1 year ago
    • Processors
    • Processors forum
  • DRA829J: How to implement the sleep & wake-up function of MCU_ONLY based on the DRA829J platform?

    pingping liu
    pingping liu
    TI Thinks Resolved
    Part Number: DRA829J Other Parts Discussed in Thread: UNIFLASH , TDA4VM Tool/software: Hi, Sir How to enter and exit the MCU_ONLY mode? Could you please provide a DEMO example? Thank you. Regards, liupingping
    • 11 months ago
    • Processors
    • Processors forum
  • Answered
  • DRA829J: Functional clock for R5F subsystems from MAIN domain

    Antonio Pinto
    Antonio Pinto
    Resolved
    Part Number: DRA829J Tool/software: Dear TI-Team, While checking the TRM for the functional clock sources of R5FSS0 and R5FSS1, we realized that in the integration diagram there's a CTRL_MMR0 register to select the clock source. However, when checking…
    • Resolved
    • 4 months ago
    • Processors
    • Processors forum
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