Part Number: DRA829J-Q1 Other Parts Discussed in Thread: DRA829 I am designing the DRA829 power sequencing (combined mode).
In the event of a power failure, I can guarantee the processors POR gets pulled low, but I may not be able to guarantee the exact…
Part Number: DRA829J-Q1 Hi Team, The goal is to make domain segregation between MCU and MAIN domain, MCU need to reach a high level of functional safety. Regarding C7x boot:
-> It is possible to boot DSPs (C7x/C66x) entirely from MCU_R5F and hide it…
Part Number: DRA829J-Q1 Other Parts Discussed in Thread: DRA829 In the DRA829 datasheet, the combined power up sequencing (Figure 6-3) shows the following clocks as:
WKUP_OSC0_XI, WKUP_OSC1_XO WKUP_LFOSC0_XI, WKUP_LFOSC0_XO (optional) OSC1_XI, OSC1_XO…
Part Number: DRA829J-Q1 Hi,
I´m using an MRAM on MCSPI0 with. My Clock settings are MCSPI_CHCONF_0[CLKG]=1bin MCSPI_CHCONF_0[CLKD]=0010bin MCSPI_CHCONF_0[POL]=0bin MCSPI_CHCONF_0[PHA]=0bin MCSPI_CHCTRL_0[EXTCLK]=0bin
Resulting Fratio is 3 in this…
Part Number: DRA829J-Q1 Hello,
Table 5-125 of SPRSP35K gives the link between Ball Number and PADCONFIG Register.
Following Registers are not listed in this table but in SPRUIL1 Table 6-2:
CTRLMMR_PADCONFIG18, CTRLMMR_PADCONFIG171, CTRLMMR_PADCONFIG172…
Hello,
franziskus said: 1. Is this a known behavior of the CCS 10.x unattended installer under LocalSystem?
I am not aware of such an issue with that version of the installer
franziskus said: 2. Is there a flag to disable the `CCSExternalReferences…
Part Number: DRA829J-Q1 Other Parts Discussed in Thread: DRA829 , TDA4VM
Team, Is the a public document available describing the operation of VBUSM and VBUSP for the J721E device? (something comparable to the ARM AXI specification : https://developer…
Part Number: DRA829J-Q1 I am searching for data about long-term stability of Jacinto internal structures. Especially information about the stability of factory programmed data (e.g. AVS calibration in WKUP_VTM_VD_OPPVID registers) and firmware (boot ROM…
Part Number: DRA829J-Q1 I am searching for data about long-term stability of Jacinto internal structures. Especially information about the stability of factory programmed data (e.g. AVS calibration in WKUP_VTM_VD_OPPVID registers) and firmware (boot ROM…
Part Number: DRA829J-Q1 Tool/software: We use PCIe (SERDES0 and SERDES2) of DRA829J-Q1 with Gen1, Jacinto is root complex.
Our design uses differential PCIE_REFCLK pins in Output REFCLK Mode to clock the end point, as described in SPRACP4A.
External…
