Part Number: DRA829V
Tool/software:
Dear TI team, Working on a 2-L SerDes driver for the PCIe subsystem, I am not sure about the right register initialization sequence and recommended register settings, apart from default values. This information can…
Hi,
Doredla Sudheer Kumar said: IPC vring (IPC_VRING_MEM) memory using in MCU2_0 is different from MCU2_1. MCU2_1 if it is as per TI SDK: 0XA4000000 - 8MB MCU2_0 it was SHARED_DDR_SPACE_START 0xAA000000 /* 0xAA000000 */
As informed the IPC VRING is different…
Part Number: DRA829V Tool/software: Dear TI team, In the TRM ( J721E_registers4) the offset of this register is defined as 'Offset = 400800h + (k * 8h); where k = 0h to 2h'. What exactly does 'k' stand for? According to my understanding, in…
Part Number: DRA829V Tool/software: Dear TI team, Referring to the RC mode PCIe core register PCIE_CORE_RP_I_RC_BAR_0 (physical address: 0x0E000010) of the TRM (J721E_registers4), I have the following questions:
What is the difference between the register…
Hi,
Would you please send me your k3-j721e-common-proc-board.dts file and the entire MCU and MAIN Logs?
Could you please let me know the version of the SDK you use for both RTOS and Linux?
Regards,
Karthik
Part Number: DRA829V Tool/software: Hi,
I am trying to simulate the overrun error for UART to test error handling. I am using UART in FIFO polling mode. Hardware flow control( Auto CTS and Auto RTS) is disabled during initialization.
Unfortunately as…
Hi Satya,
VENU HD said: yes it is working fine with above change, previously POR6 and PORT8 are working fine so i haven't expected this index issue.
Thank you very much.
Thanks for the confirmation. Will be closing this thread. If you have any issues…
Jakob,
Yes, there should be no need to configure this register outside of what was recommended by TI/Cadence. The override you see that is different from the default comes from the IP vendor, and we suggest having that set and not changing it.
