Part Number: DS250DF230 Other Parts Discussed in Thread: DS125DF1610 , Hi,
Is Register Address 0xFD in Step 3 of Table 7-62 of the Programmer's Guide a necessary step? Also, what is the purpose of Step 0xFD?
Since 0xFD is set in the Global Registers…
Part Number: DS250DF230
Dear TI team,
First of all, because of trouble with the PCB routing, I want to swap the positive and negative pins. Is this possible?
Like capture below, Connecting SOC_TX_N to DS250DF230 's RX0P and SOC_TX_P to DS250DF230's…
Part Number: DS250DF230 Hi Team,
Please advise me on my questions bellows.
I want to distinguish if the input data is lower or higher then 4.9 Gbps.
Q1. Can PPM counter be used as a rate indicator?
Q2. If yes, are there any recommended register set up…
Part Number: DS250DF230 Hi,
The customer has configured the Retimed and Raw outputs to switch depending on the input data rate.
At this time, is there a register to check whether the output data is Retimed output or Raw output?
Best Regards,
Nishie
Part Number: DS250DF230 Hi Team,
Please advices me on my question.
The DS250DF230 datasheet insit that this devcie suport Normal Lock mode and Fast Lock mode.
However, I cann't find way to swtich these two modes.
Can you let me know hoy to swtich…
Part Number: DS250DF230 Hi, TI support team
I have received request for design guide materials.
Customer name : HUMAX NETWORKS (HUMAX)
It is confirmed that, other than the data in the datasheet, there are no reference circuit or lay-out guide data in…
Part Number: DS250DF230 Hi Team,
The customer uses 3 pieces of DS250DF230 at the same time:
The first chip uses CPRI 9.8304Gbps or 24.33.24Gbps, and the CAL_CLK_IN of the chip is connected to the 30.72MHz clock
The second chip uses 25Gbps, and the CAL_CLK_IN…
Part Number: DS250DF230 Dear TI experts,
Our project use DS250DF230 as retimer. We plan to use the internal PRBS function to test the design. Here is the connection loop:
FPGA --> channel 1 Rx
channel 1 Tx --> channel 0 Rx (with SFP module loopback…
Part Number: DS250DF230
Hi, I'm using the DS250DF230 chip, and I need to generate a 10.31G PRBS31 signal on the TX side. However, adjusting it according to "Programmer's guide(SNLU182D)" didn't work for me. So I wanted to ask how to adjust the registers…
Part Number: DS250DF230
Question 1: The data rate we designed this time is 11.181G, which is not in this table. Then what should the actual recovery clock be? Or is there any way to figure it out?
Question 2: See in the table, the recovery clock…
