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Showing 44 results View by: Thread Post Sort by
  • RE: DS90C187: LVDS serial bit delay time

    Jonathan Nguyen
    Jonathan Nguyen
    Kawai-san, Unfortunately, it seems that this parameter was only spec'd for a typical value. I was unable to find any data suggesting what the max value for this parameter may be. As stated in a previous thread, I am working on getting an EVM to…
    • over 6 years ago
    • Interface
    • Interface forum
  • DS90C187: Asking for the DS90C187LFX pin 18B setting

    SHH
    SHH
    TI Thinks Resolved
    Part Number: DS90C187 Hi Team, customer uses TI DS90C187LFX (Digital RGB to LVDS). Customer set pin 18B to high (18bits). it has abnormal display. it should be 16 gray scale. Any suggestion for the abnormal case? Here is the normal and abnormal…
    • over 6 years ago
    • Interface
    • Interface forum
  • Answered
  • RE: DS90C187: Low to High / High to Low transition time specification

    Kawai
    Kawai
    Resolved
    Hi Jonny-san, Thanks for your continuous support. Generally if the rise/fall slope is the same, smaller the amplitude is shorter the rise/fall time should be. Customer is willing to use DS90C187. It may be tough, however, do you know if the…
    • over 6 years ago
    • Interface
    • Interface forum
  • DS90C187: pin CNTL

    loic roulin
    loic roulin
    Answer Suggested
    Part Number: DS90C187 Other Parts Discussed in Thread: DS90CR286 Hi, I have seen in your datasheet pin named CNTRL (L/R) but what is goal of this pin ? and what is pin number ? thnaks best regards
    • over 8 years ago
    • Interface
    • Interface forum
  • Answered
  • RE: DS90C187: Low to High / High to Low transition time specification -> Lane to Lane variation

    Kawai
    Kawai
    Resolved
    Hi Lee-san, Thank you for your comment. Best Regards, Kawai
    • over 6 years ago
    • Interface
    • Interface forum
  • Answered
  • DS90C187 / Signal input timing

    S.Satoshi
    S.Satoshi
    Resolved
    Other Parts Discussed in Thread: DS90C187 Hi, Please let me ask about signal input timing at DS90C187. Can you accept if the RGB signal input before IN_CLK and PDB? Of course the VDD is applied before RGB signal at this case. Your comment will be…
    • Resolved
    • over 9 years ago
    • Interface
    • Interface forum
  • DS90C187: Monitor LVDS data for Automotive safety function

    Jason Liu3
    Jason Liu3
    Part Number: DS90C187 Dear Experts, My customer plans to use DS90C187 for the RGB to LVDS covert to connect the Display: There is a question to ask that can we have some hardware module inside this IC to monitor the LVDS data so that we can have…
    • over 8 years ago
    • Interface
    • Interface forum
  • Answered
  • DS90C187 / Shut-off LVDS outputs

    S.Satoshi
    S.Satoshi
    Resolved
    Other Parts Discussed in Thread: DS90C187 Hi Everyone, I understand that the LVDS outputs of DS90C187 will stay to Vos during sleep mode as attached. Now our customer is asking us the way to shut-off it (down to zero voltage) LVDS output because the…
    • Resolved
    • over 10 years ago
    • Interface
    • Interface forum
  • Answered
  • DS90C187 / Minimum transition time of TCIT and TXIT

    S.Satoshi
    S.Satoshi
    Resolved
    Other Parts Discussed in Thread: DS90C187 Hi Everyone, Let me ask about minimum transition time of TCIT and TXIT. Generally I understand that maximum time should be defined for such transition time. But now I'd like to know the reason you define the…
    • Resolved
    • over 9 years ago
    • Interface
    • Interface forum
  • Answered
  • DS90C187 / Question about Data Enable signal

    S.Satoshi
    S.Satoshi
    Resolved
    Hi Everyone, Let me ask about Data Enable signal as below. Please let me know about timing requirement from DE rising edge to INA/Bn and IN_CLK (see attached) Can the signal that is synchronous with Horizontal Sync signal use as DE signal ? …
    • Resolved
    • over 10 years ago
    • Interface
    • Interface forum
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